TEMPERATURE COMPENSATION METHOD FOR HIGH-DENSITY FLOATING-GATE MEMORY

• US 20150008496A1
• Filed: 11/27/2012
• Published: 01/08/2015
• Est. Priority Date: 12/02/2011
• Status: Active Grant

• Current Assignee: The Board of Trustees of Michigan State University (Michigan State University)
• Original Assignee: The Board of Trustees of Michigan State University (Michigan State University)
• Inventors: Chakrabartty, Shantanu, Gu, Ming, Huang, Chenling
• Granted Patent: US 9,437,602 B2
• Time in Patent Office: Days
• US Class Current: 257/298
• CPC Class Codes: G11C 16/0408 comprising cells containing floating gate transistors G11C16/0483, G11C16/0491 take precedence
• CPC Class Codes: G11C 16/0441 comprising cells containing multiple floating gate devices, e.g. separate read-and-write FAMOS transistors with connected floating gates
• CPC Class Codes: G11C 27/005 with non-volatile charge storage, e.g. on floating gate or MNOS
• CPC Class Codes: G11C 27/028 Current mode circuits, e.g. switched current memories
• CPC Class Codes: G11C 7/04 with means for avoiding disturbances due to temperature effects
• CPC Class Codes: H01L 27/0629 in combination with diodes, or resistors, or capacitors
• CPC Class Codes: H01L 28/40 Capacitors
• CPC Class Codes: H10B 41/40 characterised by the peripheral circuit region

Abstract

A temperature compensation technique is provided for a non-volatile memory arrangement. The memory arrangement includes: a memory circuit (12) having a floating gate transistor (P3) operating in weak-inversion mode and a varactor (C_v) with a terminal electrically coupled to a gate node of the floating gate transistor; a first current reference circuit (14) having a floating gate transistor (PI); a second current reference circuit (16) having a floating gate transistor (P2); and a control module (18) configured to selectively receive a reference current (I₁, I₂) from a drain of the floating gate transistor in each of the first and second current reference circuits. The control module operates to determine a ratio between the reference currents received from the first and second current reference circuits, generate a tuning voltage (V_x) in accordance with the ratio between the reference currents and apply the tuning voltage to the varactor in the memory circuit.

Claims

1. A non-volatile memory arrangement, comprising:

a first memory circuit having a floating gate transistor with a gate node and operating in weak-inversion mode, and a varactor with first terminal electrically coupled to the gate node of the floating gate transistor; and

a control module electrically coupled to a second terminal of the varactor and operable to tune a voltage applied to the varactor, thereby compensating for temperature changes.

2. The non-volatile memory arrangement of claim 1 wherein the varactor is further defined as a metal-oxide semiconductor capacitor operating in accumulation mode.

3. The non-volatile memory arrangement of claim 1 wherein the first memory circuit further includes a tunneling capacitor coupled electrically to the gate node of the floating gate transistor and a control-gate capacitor coupled electrically to the gate node of the floating gate transistor, wherein the tunneling capacitor configured to receive an injection current for the first memory circuit.

4. The non-volatile memory arrangement of claim 1 further comprises a first current reference circuit and a second current reference circuit, the first and second current reference circuit each having a floating gate transistor operating in a weak-inversion mode and a varactor having a first terminal electrically coupled to a gate node of the floating gate transistor.

5. The non-volatile memory arrangement of claim 4 wherein the control module is configured to receive a reference current from a drain of the floating gate transistor in each of the first and second current reference circuits, the control module operates to selectively determine a ratio between the reference currents received from the first and second current reference circuits and determine a tuning voltage in accordance with the ratio between the reference currents.

6. The non-volatile memory arrangement of claim 5 wherein the control module applies the tuning voltage to a second terminal of the varactor in the first memory circuit.

7. The non-volatile memory arrangement of claim 6 wherein the control module applies the tuning voltage to a first terminal of the varactor in each of the first and second current reference circuits.

8. The non-volatile memory arrangement of claim 5 further comprises a second memory circuit having a floating gate transistor operating in weak-inversion mode and a varactor with a first terminal electrically coupled to a gate node of the floating gate transistor, wherein the control module applies the tuning voltage to a second terminal of the varactor in the second memory circuit.

9. A non-volatile memory arrangement, comprising:

a first memory circuit having a floating gate transistor with a gate node and operating in weak-inversion mode, and a varactor with a first terminal electrically coupled to the gate node of the floating gate transistor;

a first current reference circuit having a floating gate transistor operating in a weak-inversion mode and a varactor with a first terminal electrically coupled to a gate node of the floating gate transistor;

a second current reference circuit having a floating gate transistor operating in a weak-inversion mode and a varactor with a first terminal electrically coupled to a gate node of the floating gate transistor; and

a control module configured to selectively receive a reference current from a drain of the floating gate transistor in each of the first and second current reference circuits and determine a ratio between the reference currents received from the first and second current reference circuits, the control module further operates to generate a tuning voltage that maintains the ratio between the reference currents constant and applies the tuning voltage to a second terminal of the varactor in the first memory circuit.

10. The non-volatile memory arrangement of claim 9 wherein the control module further operates to adjust the tuning voltage applied to the varactor of the first memory circuit.

11. The non-volatile memory arrangement of claim 9 wherein the control module applies the tuning voltage to a first terminal of the varactor in each of the first and second current reference circuits.

12. The non-volatile memory arrangement of claim 9 wherein the first memory circuit further includes a tunneling capacitor coupled electrically to the gate node of the floating gate transistor and a control-gate capacitor coupled electrically to the gate node of the floating gate transistor, wherein the tunneling capacitor configured to receive an injection current for the first memory circuit.

13. The non-volatile memory arrangement of claim 9 wherein the varactor of the first memory circuit is further defined as a metal-oxide semiconductor capacitor operating in accumulation mode.

14. A non-volatile memory arrangement comprising:

an array of memory circuits, each memory circuit having a floating gate transistor operating in weak-inversion mode and a varactor with a first terminal electrically coupled to a gate node of the floating gate transistor;

a first current reference circuit having a floating gate transistor operating in a weak-inversion mode and a varactor with a first terminal electrically coupled to a gate node of the floating gate transistor;

a second current reference circuit having a floating gate transistor operating in a weak-inversion mode and a varactor with a first terminal electrically coupled to a gate node of the floating gate transistor; and

a control module configured to selectively receive a reference current from a drain of the floating gate transistor in each of the first and second current reference circuits and determine a ratio between the reference currents received from the first and second current reference circuits, the control module further operates to generate a tuning voltage in accordance with the ratio between the reference currents and applies the tuning voltage to the varactor of each memory circuit in the array of memory circuits.

15. The non-volatile memory arrangement of claim 14 wherein the control module applies the tuning voltage to a first terminal of the varactor in each of the first and second current reference circuits.

16. The non-volatile memory arrangement of claim 14 wherein each memory circuit further includes a tunneling capacitor coupled electrically to the gate node of the floating gate transistor and a control-gate capacitor coupled electrically to the gate node of the floating gate transistor, wherein the tunneling capacitor configured to receive an injection current for the memory circuit.

17. The non-volatile memory arrangement of claim 14 wherein the varactor for a given memory circuit in the array of memory circuits is further defined as a metal-oxide semiconductor capacitor operating in accumulation mode.