THREE DIMENSIONAL NAND DEVICE WITH BIRDS BEAK CONTAINING FLOATING GATES AND METHOD OF MAKING THEREOF

• US 20150008505A1
• Filed: 02/18/2014
• Published: 01/08/2015
• Est. Priority Date: 07/08/2013
• Status: Active Grant

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: Sandisk Technologies Incorporated (Western Digital Corporation)
• Inventors: Chien, Henry, Lee, Donovan, Purayath, Vinod R., Zhang, Yuan, Kai, James K., Matamis, George
• Granted Patent: US 9,252,151 B2
• Time in Patent Office: Days
• US Class Current: 257/324
• CPC Class Codes: H01L 27/0688 Integrated circuits having a three-dimensional layout
• CPC Class Codes: H01L 29/66825 with a floating gate H01L29/6684 takes precedence
• CPC Class Codes: H01L 29/7889 Vertical transistors, i.e. transistors having source and drain not in the same horizontal plane
• CPC Class Codes: H01L 29/7926 Vertical transistors, i.e. transistors having source and drain not in the same horizontal plane
• CPC Class Codes: H10B 41/20 characterised by three-dimensional arrangements, e.g. with cells on different height levels
• CPC Class Codes: H10B 41/27 the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 43/27 the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 43/35 with cell select transistors, e.g. NAND

Abstract

A method of making a monolithic three dimensional NAND string including forming a stack of alternating layers of a first material and a second material over a substrate. The first material comprises an electrically insulating material and the second material comprises a semiconductor or conductor material. The method also includes etching the stack to form a front side opening in the stack, forming a blocking dielectric layer over the stack of alternating layers of a first material and a second material exposed in the front side opening, forming a semiconductor or metal charge storage layer over the blocking dielectric, forming a tunnel dielectric layer over the charge storage layer, forming a semiconductor channel layer over the tunnel dielectric layer, etching the stack to form a back side opening in the stack, removing at least a portion of the first material layers and portions of the blocking dielectric layer.

Claims

1. A method of making a monolithic three dimensional NAND string, comprising:

forming a stack of alternating layers of a first material and a second material over a substrate, wherein the first material comprises an electrically insulating material and wherein the second material comprises a semiconductor or conductor material;

etching the stack to form a front side opening in the stack;

forming a blocking dielectric layer over the stack of alternating layers of a first material and a second material exposed in the front side opening;

forming a semiconductor or metal charge storage layer over the blocking dielectric;

forming a tunnel dielectric layer over the charge storage layer;

forming a semiconductor channel layer over the tunnel dielectric layer;

etching the stack to form a back side opening in the stack;

removing at least a portion of the first material layers and portions of the blocking dielectric layer through the back side opening to form back side recesses between the second material layers; and

oxidizing regions of the charge storage layer adjacent the back side recesses to form discrete charge storage regions.

2. The method of claim 1, wherein the layers of a first material comprises composite layers comprising a layer of silicon nitride between layers of silicon oxide.

3. The method of claim 1, further comprising filling the back side recesses with an insulating material.

4. The method of claim 1, wherein removing at least a portion of the first material layers leaves second material control gates contacting the blocking dielectric layer portions separated by the back side recesses.

5. The method of claim 1, wherein oxidizing regions of the charge storage layer also oxidizes surfaces of the second material exposed in the back side recesses.

6. The method of claim 1, wherein the blocking dielectric layer comprises a layer of silicon nitride between layers of silicon oxide.

7. The method of claim 1, wherein the discrete charge storage regions comprise floating gates having concave boundaries with oxidized semiconductor or metal regions of the charge storage layer.

8. The method of claim 7, wherein portions of the concave boundaries of the discrete charge storage regions comprise a bird'"'"'s peak shape.

9. The method of claim 7, wherein the second material comprises polysilicon or amorphous silicon.

10. The method of claim 9, wherein the polysilicon or the amorphous silicon is doped with at least one of carbon or boron and the floating gates comprise intrinsic polysilicon that etches faster than the doped polysilicon or doped amorphous silicon second material.

11. The method of claim 10, wherein a concentration of the at least one of carbon or boron is in the range of 10¹⁹ to 10²¹ atoms/cm³.

12. The method of claim 1, further comprising forming a protective layer over exposed portions of the second layer in the back side recesses after forming the back side recesses.

13. The method of claim 12, wherein the protective layer comprises silicon nitride.

14. The method of claim 1, further comprising forming a layer of material having a higher work function than the semiconductor or metal charge storage layer over the blocking dielectric prior to forming the charge storage layer.

15. The method of claim 14, further comprising removing at least a portion of the layer of material having the higher work function through the back side opening.

16. The method of claim 15, wherein the layer of higher work function material comprises a ruthenium or titanium nitride layer.

17. The method of claim 16, wherein the least a portion of the ruthenium layer removed is removed by oxidation and sublimation.

18. A method of making a monolithic three dimensional NAND string, comprising:

forming a stack of alternating first and second layers over a substrate, wherein the first layers comprise an electrically insulating composite layer comprising a silicon nitride layer between silicon oxide layers and wherein the second layers comprise a semiconductor or conductor material;

etching the stack to form a front side opening in the stack;

forming a blocking dielectric layer over the stack of alternating first and second layers exposed in the front side opening;

forming a charge storage layer over the layer of high work function material;

forming a tunnel dielectric layer over the charge storage layer;

forming a semiconductor channel layer over the tunnel dielectric layer;

etching the stack to form a back side opening in the stack;

removing at least a portion of the silicon nitride layer between silicon oxide layers to form back side recesses between adjacent second layers;

removing portions of the blocking dielectric layer exposed in the back side recesses; and

forming discrete charge storage regions.

19. The method of claim 18, wherein the charge storage layer comprises a semiconductor, metal or silicide charge storage layer and the method further comprises forming a layer of material having a work function higher than the semiconductor metal or silicide charge storage layer over the blocking dielectric layer prior to forming the charge storage layer.

20. The method of claim 19, further comprising removing the layers of silicon oxide of the composite layer and the layer of higher work function material exposed in the back side recesses.

21. The method of claim 19, wherein the layer of higher work function material comprises ruthenium or titanium nitride and the tunnel dielectric comprises silicon oxide.

22. The method of claim 18, wherein the charge storage layer comprises intrinsic polysilicon and the charge storage regions comprise floating gates.

23. The method of claim 18, wherein the step of forming the discrete charge storage regions comprises oxidizing the charge storage layer material exposed in the back side recesses, wherein the discrete charge storage regions comprise concave boundaries located perpendicular to the tunnel dielectric layer.

24. The method of claim 23, wherein a portion of the concave boundaries of the discrete charge storage regions comprise a bird'"'"'s peak shape.

25. The method of claim 18, wherein the step of forming the discrete charge storage regions comprises removing portions of the charge storage layer exposed in the back side recesses by etching.

26. The method of claim 25, wherein the second layers comprise polysilicon or amorphous silicon doped with at least one of carbon or boron, the charge storage layer comprises intrinsic polysilicon, and the second material layers are etched at a lower rate than the charge storage layer during the step of forming the discrete charge storage regions.

27. The method of claim 18, wherein the layers of silicon oxide in the composite layer protect the second material when removing at least a portion of the silicon nitride layer between silicon oxide layers.

28. The method of claim 18, wherein the blocking dielectric layer comprises a silicon nitride layer located between a first silicon oxide layer and a second silicon oxide layer.

29. The method of claim 28, further comprising:

removing the first oxide layer and the nitride layer of the blocking dielectric layer and the silicon oxide layers of the composite layer after removing the silicon nitride layer of the composite layer;

forming a protective layer on portions of the second material layers exposed in the back side recesses;

removing the second oxide layer of the blocking dielectric; and

forming the discrete charge storage regions by etching or oxidation of portions of the charge storage layer exposed in the back side recesses.

30. A monolithic three dimensional NAND string, comprising:

a semiconductor channel, at least one end portion of the semiconductor channel extending substantially perpendicular to a major surface of a substrate;

a plurality of control gate electrodes extending substantially parallel to the major surface of the substrate, wherein the plurality of control gate electrodes comprise at least a first control gate electrode located in a first device level and a second control gate electrode located in a second device level located over the major surface of the substrate and below the first device level;

a blocking dielectric located in contact with the plurality of control gate electrodes;

a plurality of vertically spaced apart charge storage regions located in contact with the blocking dielectric, wherein the plurality of vertically spaced apart charge storage regions comprise at least a first spaced apart charge storage region located in the first device level and a second spaced apart charge storage region located in the second device level and wherein a portion of the first and second charge storage regions comprises a bird'"'"'s beak shape; and

a tunnel dielectric located between each one of the plurality of the vertically spaced apart charge storage regions and the semiconductor channel.

31. The NAND string of claim 30, further comprising a protective layer located on portions of the control gate electrodes not in contact with the blocking dielectric.

32. The NAND string of claim 31, wherein the protective layer comprises silicon nitride.

33. The NAND string of claim 30, wherein the blocking dielectric comprises a layer of silicon nitride between layers of silicon oxide.

34. The NAND string of claim 30, wherein the first and second charge storage regions each comprise a polysilicon region having the bird'"'"'s beak shape and region of material having a higher work function than the polysilicon region.

35. The NAND string of claim 34, wherein the region of higher work function material comprises a ruthenium or titanium nitride region.

36. The NAND string of claim 30, wherein the second material comprises polysilicon doped with at least one of carbon or boron.

37. A method of making a monolithic three dimensional NAND string, comprising:

forming a stack of alternating layers of a first material and a second material over a substrate, wherein the first material comprises an electrically insulating material and wherein the second material comprises a semiconductor or conductor material;

etching the stack to form a front side opening in the stack;

forming a blocking dielectric layer over the stack of alternating layers of a first material and a second material exposed in the front side opening;

forming a charge storage layer over the blocking dielectric;

forming a tunnel dielectric layer over the charge storage layer;

forming a semiconductor channel layer over the tunnel dielectric layer;

etching the stack to form a back side opening in the stack;

removing at least a portion of the first material layers through the back side opening to form back side recesses between the second material layers;

forming a protective layer on portions of the second material layers exposed in the back side recesses;

after forming the protective layer, removing portions of the blocking dielectric layer exposed in the back side the recesses through the back side opening; and

forming discrete charge storage regions.

38. The method of claim 37, wherein the protective layer comprises a silicon nitride layer.

39. The method of claim 38, wherein:

the blocking dielectric layer comprises a silicon nitride layer located between a first silicon oxide layer and a second silicon oxide layer; and

the first layers comprise an electrically insulating composite layer comprising a silicon nitride layer between silicon oxide layers.

40. The method of claim 39, further comprising:

removing the silicon nitride layer of the composite layer;

before the step of forming the protective layer, removing the first oxide layer and the nitride layer of the blocking dielectric layer and the silicon oxide layers of the composite layer;

after the step of forming the protective layer, removing the second oxide layer of the blocking dielectric; and

forming the discrete charge storage regions by etching or oxidation of portions of the charge storage layer exposed in the back side recesses.