SEMICONDUCTOR DEVICE

• US 20150008525A1
• Filed: 06/20/2014
• Published: 01/08/2015
• Est. Priority Date: 07/05/2013
• Status: Active Grant

• Current Assignee: Sony Corporation (Sony Group Corp.)
• Original Assignee: Sony Corporation (Sony Group Corp.)
• Inventors: Fukuzaki, Yuzo, Ammo, Hiroaki
• Granted Patent: US 10,373,976 B2
• Time in Patent Office: Days
• US Class Current: 257/368
• CPC Class Codes: H01L 23/367 Cooling facilitated by shape of device H01L23/38, H01L23/40, H01L23/42, H01L23/44, H01L23/46 take precedence
• CPC Class Codes: H01L 23/3677 Wire-like or pin-like cooling fins or heat sinks
• CPC Class Codes: H01L 23/528 Geometry or layout of the interconnection structure H01L27/0207 takes precedence; algorithms G06F30/00
• CPC Class Codes: H01L 27/0207 Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 27/1211 combined with field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/78651 Silicon transistors H01L29/78606 - H01L29/78645 take precedence
• CPC Class Codes: H01L 29/8611 Planar PN junction diodes
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A semiconductor device includes: a substrate; an insulator layer provided on the substrate; a first transistor provided on the insulator layer; a semiconductor layer including a plurality of impurity regions of a first conduction type, the impurity regions forming a part of the first transistor; a heat dissipation layer; a thermal conductive layer linking the semiconductor layer and the heat dissipation layer; and an interruption structure configured to interrupt a flow of a current between the first transistor and the thermal conductive layer.

Claims

1. A semiconductor device comprising:

a substrate;

an insulator layer provided on the substrate;

a first transistor provided on the insulator layer;

a semiconductor layer including a plurality of impurity regions of a first conduction type, the impurity regions forming a part of the first transistor;

a heat dissipation layer;

a thermal conductive layer linking the semiconductor layer and the heat dissipation layer; and

an interruption structure configured to interrupt a flow of a current between the first transistor and the thermal conductive layer.

2. The semiconductor device according to claim 1, further comprising a second transistor provided on the insulator layer, as the interruption structure,

wherein the impurity region of the first conduction type also forms a part of the second transistor, and

the thermal conductive layer links the impurity region of the first conduction type in the second transistor, with the heat dissipation layer.

3. The semiconductor device according to claim 2, wherein the first transistor is provided between a pair of second transistors each equivalent to the second transistor, in an in-plane direction.

4. The semiconductor device according to claim 2, wherein

a plurality of first transistors each equivalent to the first transistor are arranged in a first direction, and

a pair of second transistors each equivalent to the second transistor are disposed at both ends with the plurality of first transistors interposed therebetween, in the first direction.

5. The semiconductor device according to claim 4, wherein

the first transistor and the second transistor each include a source electrode, a drain electrode, and a gate electrode, the source electrode and the drain electrode each being connected to the impurity region of the first conduction type, the gate electrode being provided in a channel region with a gate insulating film interposed therebetween, and the channel region being provided between the plurality of impurity regions of the first conduction type, and

the thermal conductive layer is connected to the source electrode or the drain electrode in the second transistor.

6. The semiconductor device according to claim 5, wherein an electric potential causing the second transistor to be in an OFF state is applied to the gate electrode in the second transistor.

7. The semiconductor device according to claim 1, wherein

the substrate also serves as the heat dissipation layer, and

the thermal conductive layer is connected to the substrate, in a region except a region in which the substrate and the semiconductor layer overlap each other.

8. The semiconductor device according to claim 1, wherein

the substrate also serves as the heat dissipation layer, and

the thermal conductive layer links the semiconductor layer and the substrate, by passing through the insulator layer.

9. The semiconductor device according to claim 1, wherein one or more metal layers are provided as the heat dissipation layer.

10. The semiconductor device according to claim 1, wherein

the semiconductor layer includes an impurity region of a second conduction type, as the interruption structure, and

the thermal conductive layer links the impurity region of the second conduction type, with the heat dissipation layer.

11. The semiconductor device according to claim 10, wherein the first transistor is provided between a pair of impurity regions each equivalent to the impurity region of the second conduction type, in an in-plane direction.