MEMS PRESSURE SENSORS AND FABRICATION METHOD THEREOF

• US 20150008541A1
• Filed: 12/03/2013
• Published: 01/08/2015
• Est. Priority Date: 07/03/2013
• Status: Active Grant

• Current Assignee: Semiconductor Manufacturing International (Shanghai) Corporation (Semiconductor Manufacturing International Corporation)
• Original Assignee: Semiconductor Manufacturing International (Shanghai) Corporation (Semiconductor Manufacturing International Corporation)
• Inventors: HONG, ZHONGSHAN
• Granted Patent: US 9,029,212 B2
• Time in Patent Office: Days
• US Class Current: 257/415
• CPC Class Codes: B81B 2201/0264 Pressure sensors
• CPC Class Codes: B81B 2203/0392 profiles not provided for in B81B2203/0376 - B81B2203/0384
• CPC Class Codes: B81B 2203/04 Electrodes
• CPC Class Codes: B81B 3/0021 Transducers for transforming electrical into mechanical energy or vice versa dynamo-electric machines H02K99/00; electrostatic machines H02N1/00; piezoelectric devices H10N30/00
• CPC Class Codes: B81B 7/007 Interconnections between the MEMS and external electrical signals
• CPC Class Codes: B81C 1/00166 Electrodes
• CPC Class Codes: B81C 1/00182 Arrangements of deformable or non-deformable structures, e.g. membrane and cavity for use in a transducer
• CPC Class Codes: G01L 9/0073 using a semiconductive diaphragm

Abstract

A MEMS capacitive pressure sensor is provided. The pressure sensor includes a substrate having a first region and a second region, and a first dielectric layer formed on the substrate. The pressure sensor also includes a first electrode layer formed on the first dielectric layer, and a second dielectric layer having first openings formed on the first electrode layer. Further, the pressure sensor includes conductive sidewalls connecting with the first electrode layer formed on sidewalls of the first openings, and a second electrode layer with a portion formed on the second dielectric layer in the second region and the rest suspended over the conductive sidewalls in the first region. Further, the pressure sensor also includes a chamber between the conductive sidewalls and the second electrode layer; and a third dielectric layer formed on the second electrode layer exposing a portion of the second electrode layer in the first region.

Claims

1. A MEMS capacitive pressure sensor, comprising:

a substrate having a first region and a second region;

a first dielectric layer formed on one surface of the substrate;

a first electrode layer formed on the first dielectric layer;

a second dielectric layer formed on the first electrode layer and having a plurality of first openings;

a plurality of conductive sidewalls connecting with the first electrode layer on sidewalls of the first openings;

a second electrode layer with a portion formed on the second dielectric layer in the second region and the rest suspended over the conductive sidewalls in the first region, causing a chamber between the conductive sidewalls and the second electrode layer; and

a third dielectric layer on the second electrode layer exposing a portion of the second electrode layer in the device region.

2. The MEMS capacitive pressure sensor according to claim 1, wherein:

the first region is a device region; and

the second region is a peripheral region

3. The MEMS capacitive pressure sensor according to claim 1, wherein the chamber is formed by:

forming a sacrificial layer on a surface of the second dielectric layer and surfaces of the conductive sidewalls;

removing a portion of the sacrificial layer on the surface of the second dielectric layer in the peripheral region;

forming a second electrode layer with a plurality of third opening exposing the sacrificial layer; and

removing the sacrificial layer by an etching process through the third openings.

4. The MEMS capacitive pressure sensor according to claim 1, further including:

a first conductive via connecting with the first electrode layer and a second conductive via connecting with the second electrode layer in the third dielectric layer in the peripheral region.

5. The method according to claim 1, wherein the substrate further includes:

a plurality of semiconductor devices and electrical interconnection structures inside and/or on one surface.

6. The MEMS capacitive pressure sensor according to claim 1, further including:

a fourth dielectric layer utilized as an etching stop layer on the second electrode layer.

7. The MEMS capacitive pressure sensor according to claim 1, wherein:

a projection of the first openings on the second dielectric layer is a plurality of concentric circles, a plurality of concentric squares, or a plurality of concentric polygons.

8. The MEMS capacitive pressure sensor according to claim 1, wherein:

a projection of the first openings on the second dielectric layer is a plurality of parellel strips.

9. The MEMS capacitive pressure sensor according to claim 1, wherein:

a number of the first openings is equal to, or greater than one.

10. The MEMS capacitive pressure sensor according to claim 1, wherein:

the first electrode layer is made of one or more of TiN, Ti, TaN, Ta, W, TiC, TaC, La, Al and Cu; and

the second electrode layer is made of one or more of TiN, Ti, TaN, Ta, W, TiC, TaC, La, Al, and Cu.

11. The MEMS capacitive pressure sensor according to claim 1, wherein:

the first dielectric layer is made of SiO₂, SiN, SiON, SiCN or low dielectric constant material;

the second dielectric layer is made of SiO₂, SiN, SiON, SiCN or low dielectric constant material; and

the third dielectric layer is made of SiO₂, SiN, SiON, SiCN or low dielectric constant material.

12. The MEMS capacitive pressure sensor according to claim 3, wherein:

the semiconductor devices are CMOS devices.

13. A method for fabricating a MEMS capacitive pressure sensor, comprising:

providing a substrate having a first region and a second region;

forming a first dielectric layer one the substrate;

forming a first electrode layer on the first dielectric layer;

forming a second dielectric layer on the first electrode layer;

etching the second dielectric layer until the first electrode layer is exposed to form a plurality of first openings;

forming a plurality of conductive sidewalls connecting with the first electrode layer on sidewalls of the first openings;

forming a sacrificial layer on a surface of the second dielectric layer in the peripheral region, surfaces of the conductive sidewalls and surfaces of the bottoms of the first openings;

forming a second electrode layer with a plurality of third openings exposing a portion of the sacrificial layer on the sacrificial layer;

removing the sacrificial layer to form a chamber between the conductive sidewalls and the second electrode layer in the first region; and

forming a third dielectric layer with a second opening exposing the surface of a portion of the second electrode layer in the first region on the second electrode layer.

14. The method according to claim 13, wherein:

the first region is a device region; and

the second region is a peripheral region.

15. The method according to claim 14, after forming the third dielectric layer, further including:

forming a second conductive via connecting with the second electrode layer in the third dielectric layer in the peripheral region; and

forming a first conductive via connecting with the first electrode layer in the third dielectric layer in the peripheral region.

16. The method according to claim 13, before forming the third dielectric layer, further including:

forming a fourth dielectric layer on the second electrode layer.

17. The method according to claim 13, before forming the second dielectric layer, further including:

forming an etching stop layer on the first dielectric layer.

18. The method according to claim 14, after forming the sacrificial layer, further including:

removing a portion of the sacrificial layer on the second dielectric layer in the peripheral region.

19. The method according to claim 13, after forming the conductive sidewalls, further including:

removing the first electrode layer on bottoms of the first openings until the first dielectric layer is exposed.

20. The method according to claim 13, wherein forming the third dielectric layer further includes:

forming the third dielectric layer on a surface of the second dielectric layer and a surface of the second electrode layer; and

etching the third dielectric layer in the device region until the surface of the second electrode layer in the device region is exposed.