VOLUME SELECT FOR AFFECTING A STATE OF A NON-SELECTED MEMORY VOLUME

• US 20150009773A1
• Filed: 07/03/2013
• Published: 01/08/2015
• Est. Priority Date: 07/03/2013
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Grunzke, Terry M.
• Granted Patent: US 9,117,504 B2
• Time in Patent Office: Days
• US Class Current: 365/230.08
• CPC Class Codes: G11C 16/08 Address circuits; Decoders; Word-line control circuits
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 5/14 Power supply arrangements , e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
• CPC Class Codes: G11C 5/147 Voltage reference generators, voltage or current regulators; Internally lowered supply levels; Compensation for voltage drops G11C5/141 takes precedence
• CPC Class Codes: G11C 5/148 Details of power up or power down circuits, standby circuits or recovery circuits
• CPC Class Codes: G11C 7/1006 Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
• CPC Class Codes: G11C 8/06 Address interface arrangements, e.g. address buffers
• CPC Class Codes: G11C 8/12 Group selection circuits, e.g. for memory block selection, chip selection, array selection

Abstract

Apparatuses and methods of operating memory are described. One such method can include receiving a select command at a plurality of memory volumes of a memory device, the select command indicating a targeted memory volume of the plurality of memory volumes. In response to the select command, the method can include selecting the targeted memory volume of the memory volumes and putting at least a portion of a non-selected memory volume of the memory volumes in a particular state based, at least in part, on a previous state of the non-selected memory volume and/or a portion of an address associated with the select command.

Claims

1. A method of operating memory, comprising:

receiving a select command at a plurality of memory volumes of a memory device, the select command indicating a targeted memory volume of the plurality of memory volumes; and

responsive to the select command;

selecting the targeted memory volumes; and

putting at least a portion of a non-selected memory volume of the plurality of memory volumes in a particular state based, at least in part, on a previous state of the at least portion of the non-selected memory volume.

2. The method of claim 1, wherein receiving the select command comprises receiving a volume select command and an associated address, wherein the associated address indicates the targeted memory volume of the plurality of volumes.

3. The method of claim 1, wherein the previous state comprises an active state, and wherein the active state uses more power than the particular state.

4. The method of claim 1, wherein, putting at least the portion of the non-selected memory volume in the particular state comprises reverting the non-selected memory volume to an inactive state.

5. The method of claim 1, comprising activating the plurality of memory volumes responsive to an enable signal switching from a first state to a second state.

6. The method of claim 1, wherein selecting the targeted memory volume comprises keeping the targeted memory volume in an active state.

7. The method of claim 1, wherein putting the at least portion of the non-selected memory volume in the particular state comprises deactivating page buffers and input buffers of the non-selected memory volume.

8. A method of operating memory, comprising:

receiving a select command and an associated select address at a plurality of memory volumes of a memory device, wherein a first portion of the select address indicates a targeted memory volume of the plurality of memory volumes;

selecting the targeted memory volume responsive to the select command and the first portion of the select address; and

putting at least a portion of a non-selected memory volume of the plurality of memory volumes in a particular state based, at least in part, on a second portion of the select address.

9. The method of claim 8, comprising transmitting the first portion of the select address and the second portion of the select address as a single select address.

10. The method of claim 8, comprising transmitting the first portion of the select address as a first select address and the second portion of the select address as second address.

11. The method of claim 8, wherein the particular state comprises a first reduced power state;

and

wherein the method comprises putting at least a portion of a non-selected memory volume of the plurality of memory volumes of the memory device that is not activated in a second reduced power state responsive to the select command.

12. The method of claim 11, wherein the first reduced power state is a lower power state than the second reduced power state, and wherein the first reduced power state and second reduced power state are lower power states than an active state.

13. The method of claim 8, wherein the second portion of the select address comprises a bit-map for at least a portion of non-selected memory volume to indicate whether the at least portion of the non-selected memory volume of the plurality of memory volumes will be put in the particular state.

14. The method of claim 8, comprising assigning at least a portion of each of the plurality of memory volumes of the memory device during initialization to enter the particular state or not when the select command is issued and the at least portion of the memory volume is on a non-selected memory volume.

15. The method of claim 14, further comprising assigning the at least portion of each of the plurality of memory volumes of the memory device during initialization to enter the particular state or not when a particular memory volume is selected.

16. The method of claim 8, wherein putting the at least portion of the non-selected memory volume of the plurality of memory volumes in the particular state based, at least in part, on the second portion of the select address further comprises putting the at least portion of the non-selected memory volume in a reduced power state based, at least in part, on the previous state of the at least portion of the non-selected memory volume being an active state.

17. The method of claim 16, wherein putting the at least portion of the non-selected memory volume in the particular state comprises putting a terminator memory unit of the non-selected memory volume in a pseudo reduced power state.

18. The method of claim 17, wherein putting the terminator memory unit of the non-selected memory volume in the pseudo reduced power state comprises deactivating page buffers and activating input buffers of the terminator memory unit.

19. The method of claim 17, comprising performing on die termination of the non-selected memory volume using the terminator memory unit in the pseudo reduced power state.

20. An apparatus, comprising:

a plurality of memory devices comprising a plurality of memory volumes, wherein the apparatus is configured to;

activate the plurality of memory volumes of the plurality of memory devices by switching a shared signal provided thereto from a first state to a second state;

subsequently provide a command to the plurality of memory devices;

wherein, responsive to the command indicating a targeted memory volume of the memory volumes, the targeted memory volume remains active and executes a subsequent command received; and

put at least a portion of an unselected memory volume of the plurality of memory volumes in a reduced power state responsive to an address associated with the command.

21. The apparatus of claim 20, wherein the apparatus is configured to revert each memory volume of the plurality of memory volumes to its respective state prior to switching the shared signal, responsive to the command not indicating any of the plurality of memory volumes as a targeted memory volume.

22. The apparatus of claim 20, wherein the apparatus is configured to deactivate a memory volume of the memory volumes by switching the shared signal thereto from the second state to the first state.

23. The apparatus of claim 22, wherein the shared signal is provided from a single chip enable terminal of the apparatus to a respective chip enable terminal of each of the plurality of memory devices.

24. A method of operating memory, comprising:

activating a memory device including a plurality of memory units by switching an enable signal to the plurality of memory units from a first state to a second state;

providing a command to the activated memory device, the command indicating a targeted memory unit among the plurality of memory units to remain active and execute a subsequent command; and

putting at least a portion of unselected memory units of the plurality of the memory units in a reduced power state responsive to an address associated with the command.

25. The method of claim 24, wherein the at least portion of the unselected memory units of the plurality of memory units comprises a first portion and wherein the reduced power state comprises a first reduced power state;

and

wherein the method further comprises putting a second portion of the unselected memory units of the plurality of memory units in a second reduced power state.

26. The method of claim 24, comprising:

wherein each of the plurality of memory units is mapped to a bit of the address associated with the command; and

wherein the address associated with the command indicates the at least portion of unselected memory units of the plurality of memory units are to be put in the reduced power state.

27. The method of claim 25, comprising:

wherein a plurality of bits of the address associated with the command are mapped to multiple memory units among the plurality of memory units; and

wherein the address associated with the command indicates the first portion of the unselected memory units of the plurality of memory units are to be put in the first reduced power state and the second portion of the unselected memory units of the plurality of memory units are to be put in the second power state.

28. The method of claim 24, wherein providing a command to the activated memory device comprises providing a volume address indicating the targeted memory unit and further comprising providing the address associated with the command as an additional address associated with the command.