PROCESSOR USING MINI-CORES

• US 20150012723A1
• Filed: 07/07/2014
• Published: 01/08/2015
• Est. Priority Date: 07/04/2013
• Status: Abandoned Application

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: PARK, Young Hwan, YANG, Ho, PRASAD, Keshava, LEE, Yeon Bok
• Application Number:
  US14/324,302
• Publication Number:
  US 20150012723A1
• Time in Patent Office: Days
• US Class Current: 712/3
• CPC Class Codes: G06F 15/7867 with reconfigurable architecture
• CPC Class Codes: G06F 9/30032 Movement instructions, e.g. MOVE, SHIFT, ROTATE, SHUFFLE
• CPC Class Codes: G06F 9/30036 Instructions to perform operations on packed data, e.g. vector, tile or matrix operations
• CPC Class Codes: G06F 9/30189 according to execution mode, e.g. mode flag
• CPC Class Codes: G06F 9/3851 from multiple instruction streams, e.g. multistreaming
• CPC Class Codes: G06F 9/3887 controlled by a single instruction for multiple data lanes [SIMD]
• CPC Class Codes: G06F 9/3891 organised in groups of units sharing resources, e.g. clusters
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A mini-core and a processor using such a mini-core are provided in which functional units of the mini-core are divided into a scalar domain processor and a vector domain processor. The processor includes at least one such mini-core, and all or a portion of functional units from among the functional units of the mini-core operate based on an operation mode.

Claims

1. A mini-core comprising:

a scalar domain processor configured to process scalar data;

a vector domain processor configured to process vector data; and

a pack/unpack functional unit (FU) configured to be shared by the scalar domain processor and the vector domain processor, and to process a conversion of data to be transmitted between the scalar domain processor and the vector domain processor.

2. The mini-core of claim 1, wherein the scalar domain processor comprises a scalar FU configured to process scalar data.

3. The mini-core of claim 1, wherein the pack/unpack FU is configured to convert multiple instances of scalar data to an instance of vector data, and to generate an instance of scalar data by extracting an element at a predetermined position of the vector data.

4. The mini-core of claim 1, wherein the vector domain processor comprises:

a vector load (LD)/store (ST) FU configured to process loading and storing of vector data; and

a vector FU configured to process the vector data.

5. The mini-core of claim 4, wherein the vector domain processor comprises vector FUs and the vector domain processor operates by interconnecting the vector FUs to process vector data of a longer bit length than a bit-length processable by the vector FUs individually.

6. The mini-core of claim 4, wherein the vector domain processor further comprises:

a vector memory configured to store the vector data.

7. The mini-core of claim 1, wherein the mini-core transmits the scalar data to another mini-core via a scalar data channel, and

the mini-core transmits the vector data to the other mini-core via a vector data channel.

8. A mini-core comprising vector functional units (FUs) configured to process a calculation of vector data,

wherein the vector FUs operate by being interconnected to one another to process vector data of a longer bit-length than a bit-length processable by the vector FUs individually.

9. The mini-core of claim 8, wherein the mini-core further comprises:

a scalar domain processor configured to process scalar data;

a vector domain processor configured to process vector data; and

a pack/unpack functional unit (FU) configured to be shared by the scalar domain processor and the vector domain processor, and to process a conversion of data to be transmitted between the scalar domain processor and the vector domain processor,

wherein the vector domain processor comprises the vector FUs.

10. A processor comprising a mini-core, wherein the mini-core comprises:

a scalar domain processor configured to process scalar data;

a vector domain processor configured to process vector data; and

a pack/unpack functional unit (FU) configured to process a conversion of data to be transmitted between the scalar domain processor and the vector domain processor.

11. The processor of claim 10, wherein the processor is configured to halt an operation of the mini-core, based on an amount of calculation to be processed by the processor.

12. The processor of claim 11, wherein the processor is configured to halt an operation of the mini-core by blocking a clock provided to the mini-core, or by blocking power to the mini-core.

13. The processor of claim 10, wherein the processor is configured to assign the mini-core to threads, and to simultaneously execute the threads.

14. The processor of claim 13, wherein the processor further comprises mini-cores, and the processor is configured to assign a differing quantity of mini-cores to the threads, based on an amount of calculation required by the threads, respectively.

15. The processor of claim 10, wherein the processor is configured to operate in a very long instruction word (VLIW) mode and a coarse-grained reconfigurable array (CGRA) mode.

16. The processor of claim 15, wherein, in response to the processor operating in the VLIW mode, the processor is configured to operate in a power saving mode by halting an operation of remaining FUs, subsequent to excluding scalar FUs from the mini-core.

17. The processor of claim 15, wherein the processor is configured to support an acceleration process through operating all FUs of the mini-core when the processor operates in the CGRA mode.

18. The processor of claim 15, wherein the processor further comprises:

a central register file configured to transmit data between the VLIW mode and the CGRA mode.

19. A processor comprising mini-cores, wherein each of the mini-cores comprises:

a scalar domain processor configured to process scalar data;

a vector domain processor configured to process vector data; and

a pack/unpack functional unit (FU) configured to process a conversion of data to be transmitted between the scalar domain processor and the vector domain processor.

20. The processor of claim 19, wherein the processor is configured to allocate the mini-cores to threads, and to simultaneously execute the plurality of threads.

21. The processor of claim 20, wherein the processor is configured to assign a differing quantity of mini-cores to the threads, based on an amount of calculation required by the threads, respectively.

22. The processor of claim 19, wherein the processor suspends an operation of a portion of the mini-cores in order to save power, based on an amount of calculation to be processed by the processor.

23. The processor of claim 19, wherein the mini-cores access single vector memories.

24. The processor of claim 19, wherein the processor is configured to operate in a very long instruction word (VLIW) mode and a coarse-grained reconfigurable array (CGRA) mode.

25. The processor of claim 24, wherein the processor is configured to operate in a power saving mode by halting an operation of remaining FUs, subsequent to excluding scalar FUs from among the mini-cores, when the processor operates in the VLIW mode.