DATA PROCESSING APPARATUS HAVING SIMD PROCESSING CIRCUITRY
First Claim
1. A data processing apparatus comprising:
- single instruction multiple data (SIMD) processing circuitry configured to perform a SIMD operation on first and second SIMD operands comprising a plurality of data elements, the SIMD processing circuitry having a plurality of parallel processing lanes for processing corresponding data elements of the first and second SIMD operands;
permutation circuitry configured to perform a permutation operation on at least one source operand comprising a plurality of source data elements to generate said first and second SIMD operands, said permutation operation generating at least one of said first and second SIMD operands with at least one of a different data element size and a different data element positioning to said at least one source operand; and
an instruction decoder configured to decode SIMD instructions requiring the SIMD operation to be performed by the SIMD processing circuitry;
wherein in response to a first SIMD instruction requiring the permutation operation and identifying the at least one source operand, the instruction decoder is configured to control the permutation circuitry to perform the permutation operation on the at least one source operand to generate the first and second SIMD operands, and to control the SIMD processing circuitry to perform the SIMD operation using the first and second SIMD operands generated by the permutation circuitry; and
in response to a second SIMD instruction not requiring the permutation operation and identifying the first and second SIMD operands, the instruction decoder is configured to control the SIMD processing circuitry to perform the SIMD operation using the first and second SIMD operands identified by the second SIMD instruction, without passing the first and second SIMD operands via the permutation circuitry.
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Abstract
A data processing apparatus has permutation circuitry for performing a permutation operation for changing a data element size or data element positioning of at least one source operand to generate first and second SIMD operands, and SIMD processing circuitry for performing a SIMD operation on the first and second SIMD operands. In response to a first SIMD instruction requiring a permutation operation, the instruction decoder controls the permutation circuitry to perform the permutation operation to generate the first and second SIMD operands and then controls the SIMD processing circuitry to perform the SIMD operation using these operands. In response to a second SIMD instruction not requiring a permutation operation, the instruction decoder controls the SIMD processing circuitry to perform the SIMD operation using the first and second SIMD operands identified by the instruction, without passing them via the permutation circuitry.
23 Citations
23 Claims
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1. A data processing apparatus comprising:
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single instruction multiple data (SIMD) processing circuitry configured to perform a SIMD operation on first and second SIMD operands comprising a plurality of data elements, the SIMD processing circuitry having a plurality of parallel processing lanes for processing corresponding data elements of the first and second SIMD operands; permutation circuitry configured to perform a permutation operation on at least one source operand comprising a plurality of source data elements to generate said first and second SIMD operands, said permutation operation generating at least one of said first and second SIMD operands with at least one of a different data element size and a different data element positioning to said at least one source operand; and an instruction decoder configured to decode SIMD instructions requiring the SIMD operation to be performed by the SIMD processing circuitry; wherein in response to a first SIMD instruction requiring the permutation operation and identifying the at least one source operand, the instruction decoder is configured to control the permutation circuitry to perform the permutation operation on the at least one source operand to generate the first and second SIMD operands, and to control the SIMD processing circuitry to perform the SIMD operation using the first and second SIMD operands generated by the permutation circuitry; and in response to a second SIMD instruction not requiring the permutation operation and identifying the first and second SIMD operands, the instruction decoder is configured to control the SIMD processing circuitry to perform the SIMD operation using the first and second SIMD operands identified by the second SIMD instruction, without passing the first and second SIMD operands via the permutation circuitry. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18)
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19. A data processing apparatus comprising:
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single instruction multiple data (SIMD) processing means for performing a SIMD operation on first and second SIMD operands comprising a plurality of data elements, the SIMD processing means having a plurality of parallel processing lane means for processing corresponding data elements of the first and second SIMD operands; permutation means for performing a permutation operation on at least one source operand comprising a plurality of source data elements to generate said first and second SIMD operands, said permutation operation generating at least one of said first and second SIMD operands with at least one of a different data element size and a different data element positioning to said at least one source operand; and instruction decoding means for decoding SIMD instructions requiring the SIMD operation to be performed by the SIMD processing means; wherein in response to a first SIMD instruction requiring the permutation operation and identifying the at least one source operand, the instruction decoding means is configured to control the permutation means to perform the permutation operation on the at least one source operand to generate the first and second SIMD operands, and to control the SIMD processing means to perform the SIMD operation using the first and second SIMD operands generated by the permutation means; and in response to a second SIMD instruction not requiring the permutation operation and identifying the first and second SIMD operands, the instruction decoding means is configured to control the SIMD processing means to perform the SIMD operation using the first and second SIMD operands identified by the second SIMD instruction, without passing the first and second SIMD operands via the permutation means.
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20. A method of processing data comprising:
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decoding single instruction multiple data (SIMD) instructions requiring a SIMD operation to be performed by SIMD processing circuitry on first and second SIMD operands comprising a plurality of data elements, the SIMD processing circuitry having a plurality of parallel processing lanes for processing corresponding data elements of the first and second SIMD operands; in response to decoding a first SIMD instruction requiring a permutation operation and identifying at least one source operand comprising a plurality of source data elements, controlling permutation circuitry to perform the permutation operation on the at least one source operand to generate said first and second SIMD operands with at least one of a different data element size and a different data element positioning to said at least one source operand, and controlling the SIMD processing circuitry to perform the SIMD operation using the first and second SIMD operands generated by the permutation circuitry; and in response to decoding a second SIMD instruction not requiring the permutation operation and identifying the first and second SIMD operands, controlling the SIMD processing circuitry to perform the SIMD operation using the first and second SIMD operands identified by the second SIMD instruction, without passing the first and second SIMD operands via the permutation circuitry.
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21. A data processing apparatus comprising:
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permutation circuitry configured to perform, in response to a program instruction, a permutation operation on at least one source operand comprising a plurality of source data elements to generate at least one permuted operand comprising a plurality of permuted data elements, said permutation operation generating each of the plurality of permuted data elements of said at least one permuted operand by; (i) setting a first portion of the permuted data element to a data value of a corresponding source data element; and (ii) filling a second portion of the permuted data element with a sign-extension or zero-extension of said data value of said corresponding source data element; wherein for at least one permuted data element, the data element position within said at least one permuted operand is different to the data element position of the corresponding source data element within said at least one source operand.
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22. A data processing apparatus comprising:
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permutation means for performing, in response to a program instruction, a permutation operation on at least one source operand comprising a plurality of source data elements to generate at least one permuted operand comprising a plurality of permuted data elements, said permutation operation generating each of the plurality of permuted data elements of said at least one permuted operand by; (i) setting a first portion of the permuted data element to a data value of a corresponding source data element; and (ii) filling a second portion of the permuted data element with a sign-extension or zero-extension of said data value of said corresponding source data element; wherein for at least one permuted data element, the data element position within said at least one permuted operand is different to the data element position of the corresponding source data element within said at least one source operand.
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23. A method of processing data comprising:
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in response to a program instruction, performing a permutation operation on at least one source operand comprising a plurality of source data elements to generate at least one permuted operand comprising a plurality of permuted data elements, said permutation operation generating each of the plurality of permuted data elements of said at least one permuted operand by; (i) setting a first portion of the permuted data element to a data value of a corresponding source data element; and (ii) filling a second portion of the permuted data element with a sign-extension or zero-extension of said data value of said corresponding source data element; wherein for at least one permuted data element, the data element position within said at least one permuted operand is different to the data element position of the corresponding source data element within said at least one source operand.
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Specification