Method and system of compiling program code into predicated instructions for excution on a processor without a program counter

• US 20150012729A1
• Filed: 07/02/2013
• Published: 01/08/2015
• Est. Priority Date: 07/02/2013
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Robison, Arch D.
• Granted Patent: US 9,507,594 B2
• Time in Patent Office: Days
• US Class Current: 712/216
• CPC Class Codes: G06F 8/41 Compilation
• CPC Class Codes: G06F 9/30036 Instructions to perform operations on packed data, e.g. vector, tile or matrix operations

Abstract

A predicated instruction compilation system includes a control flow graph generation module to generate a control flow graph of a program code to be compiled into the predicated instructions to be executed on a processor that does not include any program counter. Each of the instructions includes a predicate guard and a predicate update. The compilation system also includes a control flow transformation module to automatically generate the predicate guard and an update to the predicate state on the processor. A computer-implemented method of compiling a program code into predicated instructions is also described.

Claims

1. A computer-implemented method of compiling a program code into predicated instructions, comprising:

extracting, from control flow of the program code, constraints between instructions of the program code;

solving constraint problem between the instructions by assigning a predicate vector that satisfies the constraints to each of the instructions; and

generating a predicate guard and a predicate update for each of the instructions based on the predicate vector such that the predicated instructions can be executed on a processor that does not include any program counter.

2. The method of claim 1, further comprising

computing a control flow graph of the program code;

and

extracting the constraints from the control flow graph.

3. The method of claim 1, further comprising computing constraints on predicate bits set by a programmer of the program code.

4. The method of claim 1, wherein the extracting further comprises generating a matrix of the constraints.

5. The method of claim 4, further comprising reducing multiple constraints into a single constraint if the multiple constraints occupy a single matrix element in the matrix.

6. The method of claim 2, wherein each of the predicated instructions corresponds to a hyper-edge of the control flow graph, wherein the generating the predicate guard and predicate update is performed by determining solutions for endpoints of each hyper-edge which indicates what predicate guard and predicate update need to be for a particular instruction.

7. The method of claim 1, wherein the solving constraint problem between the instructions further comprises:

setting each ensemble to all possible predicate vectors;

eliminating possibilities based on the number of incoming plus-one and minus-one constraints; and

alternating between relaxation and narrowing until each vertex has a unique bit vector.

8. The method of claim 7, wherein the relaxation removes possibilities that violate constraints and the narrowing narrows search by choosing a non-singleton ensemble from which to remove a possibility.

9. A non-transitory computer-readable medium having sequences of instructions, the sequences of instructions including instructions which, when executed, cause a processor to perform program code compilation of a program code into predicated instructions, comprising:

extracting, from control flow of the program code, constraints between instructions of the program code;

solving constraint problem between the instructions by assigning a predicate vector that satisfies the constraints to each of the instructions; and

generating a predicate guard and a predicate update for each of the instructions based on the predicate vector such that the predicated instructions can be executed on a processor that does not include any program counter.

10. The non-transitory computer-readable medium of claim 9, further comprising

computing a control flow graph of the program code;

and

extracting the constraints from the control flow graph.

11. The non-transitory computer-readable medium of claim 9, further comprising computing constraints on predicate bits set by a programmer of the program code.

12. The non-transitory computer-readable medium of claim 9, wherein the extracting further comprises generating a matrix of the constraints.

13. The non-transitory computer-readable medium of claim 12, further comprising reducing multiple constraints into a single constraint if the multiple constraints occupy a single matrix element in the matrix.

14. The non-transitory computer-readable medium of claim 9, wherein each of the predicated instructions corresponds to a hyper-edge of the control flow graph, wherein the generating the predicate guard and predicate update is performed by determining solutions for endpoints of each hyper-edge which indicates what predicate guard and predicate update need to be for a particular instruction.

15. The non-transitory computer-readable medium of claim 9, wherein the solving constraint problem between the instructions further comprises:

setting each ensemble to all possible predicate bit vectors;

eliminating possibilities based on the number of incoming plus-one and minus-one constraints; and

alternating between relaxation and narrowing until each vertex has a unique bit vector, wherein the relaxation removes possibilities that violate constraints and the narrowing narrows search by choosing a non-singleton ensemble from which to remove a possibility.

16. A predicated instruction compilation system, comprising:

a processor;

a memory coupled to the processor;

a software compiler stored on the memory and executed by the processor to compile a program code into predicated instructions, further comprising

a control flow graph generation module to generate a control flow graph of the program code to be compiled into the predicated instructions for execution on an external processor that does not include any program counter; and

a control flow transformation module to automatically generate a predicate guard and a predicate update for each of the instruction from the control flow graph such that the predicated instructions can be executed on a processor that does not include any program counter.

17. The system of claim 16, wherein the control flow transformation module further comprises:

a control flow graph receiver to receive the control flow graph of the program code;

a constraint matrix generation module coupled to the control flow graph receiver to extract, from the control flow graph, constraints between instructions of the program code and to arrange the constraints in a matrix;

a constraint problem solving module coupled to the constraint matrix generation module to solve constraint problem between the instructions expressed in the constraint matrix by assigning a predicate vector that satisfies the constraints to each of the instructions; and

a predicate guard and predicate update generation module coupled to the constraint problem solving module to generate the predicate guard and predicate update for each of the instructions based on the predicate vector.

18. The system of claim 17, wherein the constraint matrix generation module reduces multiple constraints into a single constraint if the multiple constraints occupy a single matrix element of the matrix.

19. The system of claim 17, wherein the constraint problem solving module solves constraint problem between the instructions by setting each ensemble to all possible predicate bit vectors;

eliminating possibilities based on the number of incoming plus-one and minus-one constraints; and

alternating between relaxation and narrowing until each vertex has a unique bit vector, wherein the relaxation removes possibilities that violate constraints and the narrowing narrows search by choosing a non-singleton ensemble from which to remove a possibility.

20. The system of claim 17, wherein each of the predicated instructions corresponds to a hyper-edge of the control flow graph, wherein the predicate guard and predicate update generation module generates the predicate guard and predicate update by determining solutions for endpoints of each hyper-edge which indicates what predicate guard and predicate update need to be for a particular instruction.

21. An apparatus for compiling program code into predicated instructions, comprising:

means for generating, from control flow of the program code, constraints between instructions of the program code;

means for solving constraint problem by assigning a predicate vector that satisfies the constraints to each of the instructions; and

means for generating a predicate guard and a predicate update for each of the instructions based on the predicate vector.

22. The apparatus of claim 21, further comprising

means for generating a control flow graph of the program code;

means for computing the constraints on the predicate value set by a programmer of the program code.

23. The apparatus of claim 22, wherein the means for extracting further comprises

means for generating a matrix of the constraints;

and

means for reducing multiple constraints into a single constraint if the multiple constraints occupy a single matrix element of the constraint matrix.

24. The apparatus of claim 21, wherein each of the predicated instructions corresponds to a hyper-edge of the control flow graph, wherein the means for generating the predicate guard and predicate update further comprises means for determining solutions for endpoints of each hyper-edge which indicates what predicate guard and predicate update need to be for a particular instruction.

25. The apparatus of claim 21, wherein the means for solving constraint problem between the instructions further comprises:

means for setting each ensemble to all possible predicate bit vectors;

means for eliminating possibilities based on the number of incoming plus-one and minus-one constraints; and

means for alternating between relaxation and narrowing until each vertex has a unique bit vector, wherein the relaxation removes possibilities that violate constraints and the narrowing narrows search by choosing a non-singleton ensemble from which to remove a possibility.