POWER SUPPLY DIAGNOSTIC STRATEGY

• US 20150012781A1
• Filed: 07/30/2014
• Published: 01/08/2015
• Est. Priority Date: 06/04/2013
• Status: Active Grant

• Current Assignee: TRW Automotive USLLC (Zeppelin - Stiftung der Stadt Friedrichshafen)
• Original Assignee: TRW Automotive USLLC (Zeppelin - Stiftung der Stadt Friedrichshafen)
• Inventors: Katrak, Kerfegar K.
• Granted Patent: US 10,585,772 B2
• Time in Patent Office: Days
• US Class Current: 714/37
• CPC Class Codes: G06F 11/10 Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
• CPC Class Codes: G06F 11/24 Marginal checking or other specified testing methods not covered by G06F11/26, e.g. race tests
• CPC Class Codes: G06F 11/3013 where the computing system is an embedded system, i.e. a combination of hardware and software dedicated to perform a certain function in mobile devices, printers, automotive or aircraft systems testing or monitoring of control systems or parts thereof G05B23/02
• CPC Class Codes: G06F 11/3058 Monitoring arrangements for monitoring environmental properties or parameters of the computing system or of the computing system component, e.g. monitoring of power, currents, temperature, humidity, position, vibrations thermal management in cooling arrangements of a computing system G06F1/206
• CPC Class Codes: H02H 1/0092 concerning the data processing means, e.g. expert systems, neural networks

Abstract

A power supply diagnostic strategy for discrete power supply diagnostic states is independent of the underlying memory structure. The values used in the associated algorithm are selected to ensure that random linked failures will be detected. This applies to planar memory structures with 1, 2, 4, 6, 8, 12, and 16 common lattices, or physical memory structures with individual bit dispersed memories with 1, 2, 4, 6, 8, 12, and 16 consecutive bit splices. Further, the strategy provides that the various monitored voltage tables remains distinct even with compiler optimization activated.

Claims

1. A method for diagnosing the status of an operating voltage comprising:

(a) using a processor to read an operating voltage and to determine one of the following states;

(1) “

no”

OV, “

no”

UV;

(2) “

no”

OV, “

yes”

UV;

(3) “

yes”

OV, “

no”

UV or (4) “

yes”

OV, “

yes”

UV;

(b) assigning a distinct byte value for each of the states identified in step (a), wherein the distinct values are selected having a hamming distance of at least 4; and

(c) storing an operating status value corresponding to the determined operating state in a designated memory location of the processor.

2. The method of claim 1 wherein each distinct byte value of step (b) includes a USNb and a LSNb, and wherein all of the USNbs are distinct and are selected having a hamming distance of at least 2, and all the LSNbs are distinct and are selected having a hamming distance of at least 2.

3. The method of claim 2 wherein each of the USNbs and LSNbs are chosen from an unbalanced set of nibble values.

4. The method of claim 3 wherein each of the USNbs and LSNbs are chosen for each distinct value such that they are not complements of one another.

5. The method of claim 3 wherein the unbalanced set of nibbles include hex values 1, 2, 4, 7, 8, B, D and E.

6. The method of claim 5 wherein the USNbs are selected from the group 7, B, D and E and the LSNbs are selected from the group 1, 2, 4 and 8.

7. The method of claim 6 wherein the distinct values of step (b) include 74, B2, D1 and E8.

8. The method of claim 2 wherein, prior to step (c), the distinct byte value is checked for a match with one of a group of defined values and, if there is a match, the distinct byte value is stored as the operating status value and, if there is no match, a separate “

no match”

value is stored.

9. The method of claim 1 wherein the distinct byte value of step (b) is a lower byte of a word and further including the step of assigning an upper byte value to the word, the upper byte value including a USNb and a LSNb, and wherein one of the USNb and LSNb is a monitored voltage identifier and the other one is a control/diagnostic path identifier.

10. The method of claim 9 wherein each of the USNbs and LSNbs of the upper byte are chosen from an balanced set of nibble values.

11. A method for diagnosing the status of an operating voltage comprising:

(h) using a processor to read an operating voltage and to determine one of the following control states;

(1) “

no”

OV, “

no”

UV;

(2) “

no”

OV, “

yes”

UV;

(3) “

yes”

OV, “

no”

UV or (4) “

yes”

OV, “

yes”

UV;

(i) assigning a distinct control byte value for each of the control states identified in step (a);

(j) storing an operating control status value corresponding to the determined operating state in a designated control memory location of the processor.

(k) using the processor of step (a) to read the operating voltage and to determine one of the following diagnostic states;

(1) “

no”

OV, “

no”

UV;

(2) “

no”

OV, “

yes”

UV;

(3) “

yes”

OV, “

no”

UV or (4) “

yes”

OV, “

yes”

UV;

(l) assigning a distinct diagnostic byte value for each of the states identified in step (d);

(m) storing an operating diagnostic status value corresponding to the determined operating state in a designated diagnostic memory location of the processor; and

(n) comparing the operating control status value with the operating diagnostic status value to determine whether the control voltage state read in step (a) agrees with the diagnostic voltage state read in step (d).

12. The method of claim 11 wherein each distinct control byte value of step (b) includes a USNb and a LSNb, and wherein all of the USNbs and LSNbs are distinct.

13. The method of claim 12 wherein each distinct diagnostic byte value of step (f) includes a USNb and a LSNb, and wherein all of the USNbs and LSNbs are distinct.

14. The method of claim 13 wherein the USNb and LSNb of the diagnostic byte value are mirrored with respect to the USNb and LSNb of the corresponding control byte value.

15. The method of claim 14 wherein both the USNb and LSNb of the diagnostic byte value are compared to the mirrored USNb and LSNb of the corresponding control byte value.

16. The method of claim 14 wherein only one of the USNb and LSNb of the diagnostic byte value is compared to one of the mirrored USNb and LSNb of the corresponding control byte value.

17. The method of claim 11 wherein, prior to step (c), the distinct control byte value is checked for a match with one of a group of defined control values and, if there is a match, the distinct control byte value is stored as the operating control status value and, if there is no match, a separate “

no match”

control value is stored.

18. The method of claim 11 wherein, prior to step (f), the distinct diagnostic byte value is checked for a match with one of a group of defined diagnostic values and, if there is a match, the distinct diagnostic byte value is stored as the operating diagnostic status value and, if there is no match, a separate “

no match”

diagnostic value is stored.

19. A method of analyzing a power supply system wherein a source input voltage is supplied to a first processor and an output voltage is generated by the first processor comprising:

(a) using the first processor to determine a source operating status of the source input voltage;

(b) using a second processor to determine an output operating status of the output voltage from the first processor;

(c) sending the source operating status to the second processor; and

(d) using the processor to analyze the source and output statuses to determine a system diagnosis as a function of both the source and output statuses.

20. The method of claim 19 wherein the source operating status is sent to the second processor with no checksum or cyclic redundancy check (CRC).