SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME

• US 20150014780A1
• Filed: 01/28/2014
• Published: 01/15/2015
• Est. Priority Date: 07/15/2013
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Hyung-Soon Jang, Ju-Youn Kim
• Inventors: Kim, Ju-Youn, Jang, Hyung-Soon, Youn, Jong-Mil, Ha, Tae-Won
• Granted Patent: US 9,048,219 B2
• Time in Patent Office: Days
• US Class Current: 257/369
• CPC Class Codes: H01L 21/823807 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823814 with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
• CPC Class Codes: H01L 21/823821 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 21/823842 gate conductors with different gate conductor materials or different gate conductor implants, e.g. dual gate structures
• CPC Class Codes: H01L 21/823871 interconnection or wiring or contact manufacturing related aspects
• CPC Class Codes: H01L 27/0207 Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
• CPC Class Codes: H01L 27/092 complementary MIS field-effect transistors
• CPC Class Codes: H01L 27/0922 Combination of complementary transistors having a different structure, e.g. stacked CMOS, high-voltage and low-voltage CMOS
• CPC Class Codes: H01L 27/0924 including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/0642 Isolation within the component, i.e. internal isolation
• CPC Class Codes: H01L 29/0649 Dielectric regions, e.g. SiO2 regions, air gaps
• CPC Class Codes: H01L 29/0653 adjoining the input or output region of a field-effect device, e.g. the source or drain region
• CPC Class Codes: H01L 29/161 including two or more of the elements provided for in group H01L29/16 , e.g. alloys H01L29/1604 takes precedence
• CPC Class Codes: H01L 29/165 in different semiconductor regions , e.g. heterojunctions
• CPC Class Codes: H01L 29/20 including, apart from doping materials or other impurities, only AIIIBV compounds
• CPC Class Codes: H01L 29/42364 characterised by the insulating layer, e.g. thickness or uniformity H01L29/42324 and H01L29/4234 take precedence
• CPC Class Codes: H01L 29/42372 characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out H01L29/42324 takes precedence
• CPC Class Codes: H01L 29/42376 characterised by the length or the sectional shape
• CPC Class Codes: H01L 29/495 the conductor material next to the insulator being a simple metal, e.g. W, Mo H01L29/4908, H01L29/4983 take precedence
• CPC Class Codes: H01L 29/4966 the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2 H01L29/4908, H01L29/4983 take precedence
• CPC Class Codes: H01L 29/4983 : with a lateral structure, e.g. a Polysilicon gate with a lateral doping variation or with a lateral composition variation or characterised by the sidewalls being composed of conductive, resistive or dielectric material
• CPC Class Codes: H01L 29/51 : Insulating materials associated therewith for MIS structures on thin film semiconductor H01L29/4908
• CPC Class Codes: H01L 29/513 : the variation being perpendicular to the channel plane
• CPC Class Codes: H01L 29/517 : the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate H01L29/518 takes precedence
• CPC Class Codes: H01L 29/7848 : the means being located in the source/drain region, e.g. SiGe source and drain

Abstract

A semiconductor device includes a substrate including a first active region, a second active region and a field region between the first and second active regions, and a gate structure formed on the substrate to cross the first active region, the second active region and the field region. The gate structure includes a p type metal gate electrode and an n-type metal gate electrode directly contacting each other, the p-type metal gate electrode extends from the first active region less than half way toward the second active region.

Claims

1. A semiconductor device comprising:

a substrate including a first active region, a second active region and a field region between and directly contacting the first and second active regions; and

a gate structure formed on the substrate to cross the first active region, the second active region and the field region,

wherein the gate structure includes a p-type metal gate electrode and an n-type metal gate electrode directly contacting each other,

wherein the p-type metal gate electrode is formed on the first active region and the n-type metal gate electrode is formed on the second active region, and

wherein the contact surface between the p-type metal gate electrode and the n-type metal gate electrode is closer to the first active region than to the second active region.

2. The semiconductor device of claim 1, wherein the field region has a center line equidistantly spaced apart from the first active region and the second active region, and the p-type metal gate electrode does not extend to the center line.

3. The semiconductor device of claim 1, wherein the p-type metal gate electrode includes a p-type work function adjusting layer, a first lower metal gate electrode and a first upper metal gate electrode, sequentially formed one on another, and the n-type metal gate electrode includes a second lower metal gate electrode and a second upper metal gate electrode sequentially formed one on the other, but not including the p-type work function adjusting layer.

4. The semiconductor device of claim 3, wherein the contact surface is defined by the p-type work function adjusting layer.

5. The semiconductor device of claim 3, wherein the first lower gate electrode and the second lower gate electrode are in direct contact with one another, and the first upper gate electrode and the second upper gate electrode are in direct contact with one another.

6. The semiconductor device of claim 5, further comprising an interlayer dielectric layer formed on the substrate and including a trench intersecting the first active region, the field region and the second active region, wherein the first lower gate electrode and the second lower gate electrode are formed along sidewalls and a bottom surface of the trench.

7. The semiconductor device of claim 3, wherein the first lower gate electrode and the second lower gate electrode are separated from each other by the p-type work function adjusting layer.

8. The semiconductor device of claim 1, wherein the substrate is a silicon substrate, and a silicon germanium channel layer is provided between the first active region and the p-type metal gate electrode.

9. The semiconductor device of claim 1, wherein the first active region is a pull-up transistor forming region of a static random access memory (SRAM) and the second active region is a pull-down transistor forming region of an SRAM.

10. The semiconductor device of claim 1, wherein the first active region and the second active region are a first fin type active pattern and a second fin type active pattern, respectively.

11. A semiconductor device comprising:

a substrate including a first active region, a second active region and a field region between and directly contacting the first and second active regions;

an interlayer dielectric layer formed on the substrate, including a trench intersecting the first active region, the field region and the second active region; and

a gate structure formed in the trench to intersect the first active region, the second active region and the field region and having a top surface coplanarly formed with the interlayer dielectric layer,

wherein the gate structure includes a p type metal gate electrode and an n-type metal gate electrode directly contacting each other, and a contact surface formed between the p-type metal gate electrode and the n-type metal gate electrode,

wherein the p-type metal gate electrode is formed on the first active region and the n-type metal gate electrode is formed on the second active region, and

wherein a first width ranging from the contact surface to the first active region is less than a second width ranging from the contact surface to the second active region.

12. The semiconductor device of claim 11, wherein the p-type metal gate electrode and the n-type metal gate electrode are in direct contact with one another.

13. The semiconductor device of claim 11, wherein the field region has a center line equidistantly spaced apart from the first active region and the second active region, and the contact surface is positioned between the center line and the first active region.

14. The semiconductor device of claim 11, wherein the p-type metal gate electrode includes a p-type work function adjusting layer, a first lower metal gate electrode and a first upper metal gate electrode, sequentially formed one on another, and the n-type metal gate electrode includes a second lower metal gate electrode and a second upper metal gate electrode sequentially formed one on the other, but not including the p-type work function adjusting layer.

15. The semiconductor device of claim 14, further comprising a gate dielectric layer formed between the substrate and the p-type metal gate electrode and between the substrate and the n-type metal gate electrode, and the gate dielectric layer is formed along a bottom surface of the trench, but not formed on sidewalls of the trench.

16. The semiconductor device of claim 15, wherein the p-type work function adjusting layer has a first part formed along the gate dielectric layer and a second part extending in a direction normal to the substrate and formed on the field region, and the second part of the p-type work function adjusting layer is interposed between the first lower gate electrode and the second lower gate electrode.

17. The semiconductor device of claim 14, further comprising a gate dielectric layer formed between the substrate and the p-type metal gate electrode and between the substrate and the n-type metal gate electrode, and the gate dielectric layer is formed along sidewalls and a bottom surface of the trench.

18. The semiconductor device of claim 14, wherein the p-type work function adjusting layer includes at least one of TiN and TaN.

19. A semiconductor device comprising:

a first fin type active pattern;

a second fin type active pattern adjacent to the first fin type active pattern;

an isolation layer formed between and making direct contact with the first fin type active pattern and the second fin type active pattern; and

a gate structure intersecting the first fin type active pattern, the isolation layer and the second fin type active pattern,

wherein the gate structure includes a p-type metal gate electrode and an n-type metal gate electrode directly contacting each other,

wherein the p-type metal gate electrode is formed on the first fin type active pattern, and the n-type metal gate electrode is formed on the second fin type active pattern, and

wherein a contact surface between the p-type metal gate electrode and the n-type metal gate electrode is closer to the first fin type active pattern than to the second fin type active pattern.

20. The semiconductor device of claim 19, wherein the p-type metal gate electrode includes a p-type work function adjusting layer, a first lower metal gate electrode and a first upper metal gate electrode, sequentially formed one on another, and the n-type metal gate electrode includes a second lower metal gate electrode and a second upper metal gate electrode sequentially formed one on the other, but not including the p-type work function adjusting layer, and the contact surface is defined by the p-type work function adjusting layer.

21. The semiconductor device of claim 20, wherein the first lower gate electrode and the second lower gate electrode are in direct contact with one another, and the first upper gate electrode and the second upper gate electrode are in direct contact with one another.

22. The semiconductor device of claim 20, wherein the first lower gate electrode and the second lower gate electrode are separated from each other by the p-type work function adjusting layer.

23. The semiconductor device of claim 19, wherein the first fin type active pattern is a silicon element semiconductor, and a silicon germanium channel layer is provided between the first fin type active pattern and the p-type metal gate electrode, wherein the silicon germanium channel layer is formed along at least a portion of the first fin type active pattern.

24. The semiconductor device of claim 19, wherein the first fin type active pattern includes at least one of a silicon germanium layer and a germanium layer.

25. The semiconductor device of claim 24, wherein the second fin type active pattern includes a group III-V compound semiconductor layer.

26. A semiconductor device, comprising:

a gate structure formed over sequentially arranged first active, field, and second active regions in a substrate; and

a p-type metal gate electrode in the gate structure extending from over the first active region less than half way toward the second active region.

27. The semiconductor device of claim 26, further comprising an n-type metal gate electrode in the gate structure extending from over the second active region to greater than half way toward the first active region.

28. A semiconductor device, comprising:

a gate structure formed over sequentially arranged first active, field, and second active regions in a substrate;

a p-type metal gate electrode in the gate structure extending from over the first active region; and

an n-type metal gate electrode in the gate structure extending from over the second active region, the n-type and p-type metal gate electrodes arranged to increase the threshold voltage of the semiconductor device.

29. The semiconductor device of claim 28, wherein the p-type metal gate structure extends over the first active region less than half way toward the second active region and the n-type metal gate electrode in the gate structure extends more than half way towards the first active region.

30. A memory device including the semiconductor device of claim 28.