ELECTRONIC DEVICE USING GROUP III NITRIDE SEMICONDUCTOR AND ITS FABRICATION METHOD AND AN EPITAXIAL MULTI-LAYER WAFER FOR MAKING IT

• US 20150014817A1
• Filed: 07/11/2014
• Published: 01/15/2015
• Est. Priority Date: 04/07/2006
• Status: Active Grant

• Current Assignee: Seoul Semiconductor Co., Ltd.
• Original Assignee: SixPoint Materials, Inc.
• Inventors: HASHIMOTO, TADAO
• Granted Patent: US 9,466,481 B2
• Time in Patent Office: Days
• US Class Current: 257/615
• CPC Class Codes: C23C 16/303 Nitrides
• CPC Class Codes: H01L 21/02389 Nitrides
• CPC Class Codes: H01L 21/0242 Crystalline insulating materials
• CPC Class Codes: H01L 21/0243 Surface structure
• CPC Class Codes: H01L 21/02458 Nitrides
• CPC Class Codes: H01L 21/0254 Nitrides
• CPC Class Codes: H01L 21/02584 Delta-doping
• CPC Class Codes: H01L 21/0262 Reduction or decomposition of gaseous compounds, e.g. CVD
• CPC Class Codes: H01L 21/02623 Liquid deposition
• CPC Class Codes: H01L 21/02694 Controlling the interface between substrate and epitaxial layer, e.g. by ion implantation followed by annealing
• CPC Class Codes: H01L 29/0646 PN junctions
• CPC Class Codes: H01L 29/0653 adjoining the input or output region of a field-effect device, e.g. the source or drain region
• CPC Class Codes: H01L 29/2003 Nitride compounds
• CPC Class Codes: H01L 29/201 including two or more compounds , e.g. alloys H01L29/2006 takes precedence
• CPC Class Codes: H01L 29/205 in different semiconductor regions , e.g. heterojunctions
• CPC Class Codes: H01L 29/207 further characterised by the doping material H01L29/2006 takes precedence
• CPC Class Codes: H01L 29/32 the imperfections being within the semiconductor body
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/66462 with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
• CPC Class Codes: H01L 29/7784 with delta or planar doped donor layer H01L29/7785 takes precedence
• CPC Class Codes: H01L 29/7828 : without inversion channel, e.g. vertical ACCUFETs, normally-on vertical MISFETs
• CPC Class Codes: H01L 29/8122 : Vertical transistors SIT, PBT H01L29/7722
• CPC Class Codes: H01L 29/8611 : Planar PN junction diodes
• CPC Class Codes: H01L 29/872 : Schottky diodes

Abstract

The present invention discloses an electronic device using a group III nitride substrate fabricated via the ammonothermal method. By utilizing the high-electron concentration of ammonothermally grown substrates having the dislocation density less than 10⁵ cm⁻², combined with a high-purity active layer of Ga_1-x-yAl_xIn_yN (0≦x≦1, 0≦y≦1) grown by a vapor phase method, the device can attain high level of breakdown voltage as well as low on-resistance. To realize a good matching between the ammonothermally grown substrate and the high-purity active layer, a transition layer is optionally introduced. The active layer is thicker than a depletion region created by a device structure in the active layer.

Claims

1. An epitaxial multi-layer wafer for fabricating electronic devices comprising (i) a group III nitride substrate of Ga_1-x1-y1Al_x1In_y1N (0≦

x1≦

1, 0≦

y1≦

1) having a first side and a second side opposite to the first side and (ii) an active layer of Ga_1-x2-y2Al_x2In_y2N (0≦

x2≦

1, 0≦

y2≦

1) on the first side of the group III nitride substrate, wherein;

(a) a dislocation density of the group III nitride substrate is less than about 10⁵ cm<sup>−

2</sup>;

(b) the group III nitride substrate is selected from the group consisting of (i) a group III nitride substrate having an electron concentration higher than about 10¹⁸ cm<sup>−

3</sup> and (ii) a group III nitride substrate having an oxygen concentration higher than about 10¹⁸ cm<sup>−

3</sup>;

(c) the group III nitride substrate is fabricated from a bulk crystal of Ga_1-x1-y1Al_x1In_y1N (0≦

x1≦

1, 0≦

y1≦

1) grown in supercritical ammonia;

(d) the active layer is an epitaxially deposited layer selected from the group consisting of (i) an active layer having an electron concentration lower than about 10¹⁸ cm<sup>−

3</sup> and (ii) an active layer having an oxygen concentration lower than about 10¹⁸ cm<sup>−

3</sup>;

(e) the active layer has a thickness sufficiently large that a depletion region which is formed in the active layer after fabricating the electronic device with a first electrode on the first side of the wafer and a second electrode on the second side of the wafer is outside of the substrate.

2. An epitaxial multi-layer wafer according to claim 1 wherein the active layer has an electron concentration lower than about 10¹⁶ cm⁻

3.

3. An epitaxial multi-layer wafer according to claim 2 wherein the active layer has an oxygen concentration lower than about 10¹⁶ cm⁻

3.

4. An epitaxial multi-layer wafer according to claim 1 wherein the active layer has an oxygen concentration lower than about 10¹⁶ cm⁻

3.

5. An epitaxial multi-layer wafer according to claim 1 wherein the thickness of the active layer is more than about 5 microns.

6. An epitaxial multi-layer wafer according to claim 1 and further comprising a transition layer of Ga_1-x3-y3Al_x3In_y3N (0≦

x3≦

1, 0≦

y3≦

1) between the substrate and the active layer, wherein a first side of the transition layer has a crystal lattice matched to a crystal lattice of the first side of the substrate, and wherein a second side of the transition layer has a crystal lattice matched to a crystal lattice of a first side of the active layer.

7. An epitaxial multi-layer wafer according to claim 6 wherein the transition layer is grown by a vapor phase epitaxy.

8. An epitaxial multi-layer wafer according to claim 7 wherein the transition layer is sufficiently thick to bury cracks created at the interface between the substrate and the transition layer.

9. An epitaxial multi-layer wafer according to claim 6 wherein the depletion zone extends into the transition layer.

10. An epitaxial multi-layer wafer according to claim 6 wherein the active layer is thicker than the depletion zone.

11. An epitaxial multi-layer wafer according to claim 6 wherein the transition layer is doped with an impurity which prevents diffusion of impurities contained in the substrate.

12. An epitaxial multi-layer wafer according to claim 1 which further comprises a current blocking layer between the group III nitride substrate and the active layer.

13. An epitaxial multi-layer wafer according to claim 1 wherein the active layer has a dislocation density less than about 10⁵ cm⁻

2.

14. An epitaxial multi-layer wafer according to claim 1 wherein the substrate has a sodium concentration of greater than about 10¹⁶ cm⁻

3 and the active layer contains at least 100 times less sodium than the substrate.

15. An epitaxial multi-layer wafer according to claim 1 wherein the substrate is a c plane with miscut more than about 0.1 degree and less than about 5 degree.

16. An epitaxial multi-layer wafer according to claim 1 wherein x1=x2=0 and y1=y2=0.

17. An epitaxial multi-layer wafer according to claim 16 wherein x3=0 and y3=0.

18. An electronic device comprising a multi-layer wafer according to claim 1 and said electrodes which form the depletion region outside of the group III nitride wafer over an operating range of the electronic device.

19. An electronic device comprising a multi-layer wafer according to claim 6 and said electrodes which form the depletion region outside of the group III nitride wafer over an operating range of the electronic device.

20. An electronic device comprising a multi-layer wafer according to claim 8 and said electrodes which form the depletion region outside of the group III nitride wafer over an operating range of the electronic device.