MICROELECTRONIC PACKAGES AND METHODS FOR THE FABRICATION THEREOF

• US 20150014855A1
• Filed: 07/15/2013
• Published: 01/15/2015
• Est. Priority Date: 07/15/2013
• Status: Active Grant

• Current Assignee: NXP USA, Inc. (NXP Semiconductors NV)
• Original Assignee: Douglas G. Mitchell, Weng Foong Yap
• Inventors: YAP, WENG FOONG, MITCHELL, DOUGLAS G.
• Granted Patent: US 9,018,045 B2
• Time in Patent Office: Days
• US Class Current: 257/773
• CPC Class Codes: H01L 21/56 Encapsulations, e.g. encapsulation layers, coatings
• CPC Class Codes: H01L 21/568 Temporary substrate used as encapsulation process aid H01L21/4832 and H01L21/566 take precedence
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/04105 Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
• CPC Class Codes: H01L 2224/12105 Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
• CPC Class Codes: H01L 2224/18 High density interconnect [HDI] connectors; Manufacturing methods related thereto
• CPC Class Codes: H01L 2224/24137 the bodies being arranged next to each other, e.g. on a common substrate
• CPC Class Codes: H01L 23/3128 the substrate having spherical bumps for external connection
• CPC Class Codes: H01L 23/3135 Double encapsulation or coating and encapsulation
• CPC Class Codes: H01L 23/48 Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
• CPC Class Codes: H01L 23/5389 the chips being integrally enclosed by the interconnect and support structures
• CPC Class Codes: H01L 24/19 Manufacturing methods of high density interconnect preforms
• CPC Class Codes: H01L 24/20 Structure, shape, material or disposition of high density interconnect preforms
• CPC Class Codes: H01L 24/24 of an individual high density interconnect connector
• CPC Class Codes: H01L 24/82 by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI] interconnection structure between a plurality of semiconductor chips H01L23/5389
• CPC Class Codes: H01L 24/96 the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/181 Encapsulation

Abstract

Microelectronic packages and methods for fabricating microelectronic packages are provided. In one embodiment, the method comprises encapsulating a first semiconductor die having one or more core redistribution layers formed thereover in an outer molded body. The outer molded body has a portion, which circumscribes the core redistribution layer. One or more topside redistribution layers are produced over the core redistribution layer. A contact array is formed over the topside redistribution layer and electrically coupled to the first semiconductor die encapsulated in the outer molded body through the topside redistribution layers and the core redistribution layers.

Claims

1. (canceled)

3. (canceled)

4. A method for fabricating a microelectronic package, comprising:

encapsulating a first semiconductor die having one or more core redistribution layers formed thereover in an outer molded body, the outer molded body having a portion circumscribing the core redistribution layers;

producing one or more topside redistribution layers over the core redistribution layers; and

forming a contact array over the topside redistribution layers and electrically coupled to the first semiconductor die encapsulated in the outer molded body through the topside redistribution layers and the core redistribution layers;

wherein the first semiconductor die is embedded within an inner molded body, wherein encapsulating comprises forming an outer molded body around the inner molded body and the core redistribution layers, and wherein a second semiconductor die is embedded within the inner molded body and electrically interconnected with the first semiconductor die by the core redistribution layers.

2. The method of claim 4 wherein producing comprises producing one or more topside redistribution layers to extend at least partially over the portion of the outer molded body circumscribing the core redistribution layers.

5. The method of claim 4 wherein encapsulating comprises encapsulating a microelectronic component along with the first semiconductor die, and wherein producing comprises producing the one or more topside redistribution layers to electrically couple the microelectronic component through the one or more core redistribution layers.

6. The method of claim 4 further comprising testing the first semiconductor die and the one or more core redistribution layers prior to encapsulating the first semiconductor die in the outer molded body.

7. The method of claim 4 further comprising:

processing a wafer to produce an array of semiconductor die including the first semiconductor die and the second semiconductor die; and

producing one or more core redistribution layers over the frontside of the wafer prior to singulation thereof.

8. The method of claim 4 further comprising:

prior to encapsulating the first semiconductor die in the outer molded body, overmolding an array of semiconductor die including the first semiconductor die and the second semiconductor die to produce an initial Redistributed Chip Packaging (RCP) panel;

producing the one or more core redistribution layers over the frontside of the initial RCP panel; and

singulating the initial RCP panel to produce a core package including an inner molded body in which the first semiconductor die and the second semiconductor die are embedded.

9. The method of claim 8 wherein encapsulating comprises overmolding the core redistribution layers and the core package to form the outer molded body surrounding the inner molded body.

10. The method of claim 4 wherein encapsulating comprises:

positioning the first semiconductor die, the second semiconductor die, and a plurality of other semiconductor die on a temporary substrate;

dispensing a mold compound over the first semiconductor die, the second semiconductor die, and the plurality of other semiconductor die; and

curing the mold compound to form a molded panel containing the first semiconductor die, the second semiconductor die, and the plurality of other semiconductor die.

11. A method for fabricating a microelectronic package, comprising:

encapsulating a first semiconductor die having one or more core redistribution layers formed thereover in an outer molded body, the outer molded body having a portion circumscribing the core redistribution layers;

producing one or more topside redistribution layers over the core redistribution layers; and

forming a contact array over the topside redistribution layers and electrically coupled to the first semiconductor die encapsulated in the outer molded body through the topside redistribution layers and the core redistribution layers;

wherein encapsulating comprises encapsulating the first semiconductor die and a microelectronic component within the outer molded body, and wherein producing comprises producing one or more topside redistribution layers over the core redistribution layers and electrically interconnecting the first semiconductor die and the microelectronic component.

12. The method of claim 11 wherein the microelectronic component comprises a second semiconductor die over which one or more core redistribution layers have not been formed.

13. The method of claim 11 wherein the microelectronic component comprises a passive microelectronic device, and wherein the topside redistribution layers electrically interconnect the first semiconductor die and the passive microelectronic device to produce a System-in-Package.

14. The method of claim 11 wherein the microelectronic component is encapsulated within the outer molded body at an elevation overlapping with the core redistribution layers.

15. A method for fabricating a microelectronic package, comprising:

forming a Redistributed Chip Packaging (RCP) panel containing a first microelectronic component, one or more core redistribution layers overlying and in ohmic contact with the first microelectronic component, and a second microelectronic component positioned proximate the first microelectronic component and having a portion that is coplanar in elevation with the core redistribution layers;

producing one or more topside redistribution layers over the RCP panel interconnecting the first and second microelectronic component through the core redistribution layers; and

forming a contact array over the topside redistribution layers and electrically coupled to the first and second microelectronic components.

16. The method of claim 15 wherein the first microelectronic component comprises a semiconductor die, and wherein the second microelectronic component comprises a passive microelectronic device.

17. The method of claim 15 further comprising singulating the RCP panel after forming the contact array to yield a plurality of RCP packages, one of which contains the first and second microelectronic components.

18. The method of claim 15 wherein the first microelectronic component comprises a first semiconductor die, and wherein the method further comprises:

processing a semiconductor wafer to produce an array of semiconductor die including the first semiconductor die; and

producing the core redistribution layers over the semiconductor wafer prior to singulation thereof.

19. The method of claim 15 wherein the first microelectronic component comprises a first semiconductor die, and wherein the method further comprises:

overmolding a plurality semiconductor die including the first microelectronic device to produce an initial RCP panel;

producing one or more core redistribution layers over the frontside of the initial RCP panel; and

singulating the initial RCP panel to produce a core RCP package including an inner molded body surrounding the first semiconductor die;

wherein forming comprises forming the RCP panel to contain the core RCP package and microelectronic component.

20. A microelectronic package, comprising:

a first semiconductor die;

one or more core redistribution layers formed over the first semiconductor die;

an outer molded body in which the first semiconductor die is embedded, the outer molded body having a portion extending around the core redistribution layers;

one or more topside redistribution layers formed over the core redistribution layers and the portion of the outer molded body extending around the core redistribution layers;

a microelectronic device embedded in the outer molded body and electrically coupled to the first semiconductor die through the core redistribution layers, through the topside redistribution layers, or a combination thereof; and

a contact array formed over the topside redistribution layers and electrically coupled to the first semiconductor die embedded in the outer molded body through the core redistribution layers and the topside redistribution layers.

21. The microelectronic package of claim 20 wherein the microelectronic device comprises a second semiconductor die electrically coupled to the contact array through the topside redistribution layers.

22. The microelectronic package of claim 20 wherein the microelectronic component is encapsulated within the outer molded body at an elevation overlapping with the core redistribution layers.