LOW DROPOUT VOLTAGE REGULATOR

• US 20150015222A1
• Filed: 07/09/2013
• Published: 01/15/2015
• Est. Priority Date: 07/09/2013
• Status: Abandoned Application

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments Deutschland Gesellschaft Mit Beschrã¤Nkter Haftung (Texas Instruments, Inc.), Texas Instruments, Inc.
• Inventors: Ivanov, Vadim Valerievich, Chakraborty, Sudipto, Graul, Jens
• Application Number:
  US13/938,085
• Publication Number:
  US 20150015222A1
• Time in Patent Office: Days
• US Class Current: 323/273
• CPC Class Codes: G05F 1/56 using semiconductor devices in series with the load as final control devices G05F1/461 takes precedence

Abstract

Voltage regulators are disclosed herein. An embodiment of a voltage regulator includes a MOS-type pass transistor, wherein a first node of the pass transistor is connectable to a voltage source and wherein a second node of the pass transistor is connected to the output of the voltage regulator. The voltage regulator also includes an error amplifier having a reference input and an output, the output being connected to the gate of the pass transistor, and the reference input being connected to a reference voltage source.

Claims

1. A voltage regulator comprising:

a MOS-type pass transistor, wherein a first channel of the pass transistor is connectable to a voltage source and wherein a second channel of the pass transistor is connected to the output of the voltage regulator; and

an error amplifier having a reference input and an output, the output being connected to the gate of the pass transistor, the reference input being connected to a reference voltage source.

2. The voltage regulator of claim 1 and further comprising a capacitor connected between the gate of the pass transistor and ground.

3. The voltage regulator of claim 1, wherein the closed-loop bandwidth of the error amplifier is below 20 kHz.

4. The voltage regulator of claim 1, wherein the closed-loop bandwidth of the error amplifier is below 10 kHz.

5. The voltage regulator of claim 1, wherein the pass transistor is an NMOS-type transistor and wherein the drain of the pass transistor is connectable to the voltage source and wherein the source of the pass transistor is connected to the output of the voltage regulator.

6. The voltage regulator of claim 1, wherein the pass transistor is an PMOS-type transistor and wherein the source of the pass transistor is connectable to the voltage source and wherein the drain of the pass transistor is connected to the output of the voltage regulator.

7. The voltage regulator of claim 1, wherein the error amplifier comprises an input stage and wherein the input stage comprises an AB class amplifier.

8. The voltage regulator of claim 1, wherein the current drawn by the error amplifier is proportional to the difference between the value of the reference voltage source and the voltage at the output of the regulator.

9. A voltage regulator comprising:

a pass transistor, wherein a first channel of the pass transistor is connectable to a voltage source and wherein a second channel of the pass transistor is connected to the output of the voltage regulator; and

an error amplifier having a reference input and an output, the output being connected to the gate of the pass transistor, the reference input being connected to a reference voltage source, and the error amplifier having an AB input stage.

10. The voltage regulator of claim 9, wherein the current drawn by the error amplifier is proportional to the difference between the value of the reference voltage source and the voltage at the output.

11. The voltage regulator of claim 9, wherein the input stage comprises a differential amplifier, the differential amplifier comprising:

a first transistor, wherein the reference input is connected to the gate of the first transistor;

a second transistor, wherein the output of the error amplifier is connected to the gate of the second transistor; and

a biasing transistor operative to bias current through the first transistor.

12. The voltage regulator of claim 9, wherein the input stage comprises a differential amplifier, the differential amplifier comprising:

a first feedback loop, wherein the reference input is connected to the first feedback loop; and

a second feedback loop, wherein the output of the error amplifier is connected to the second feedback loop;

wherein when the output load of the voltage regulator increases, the output voltage of the error amplifier drops and the bias current in the first feedback loop increases.

13. The voltage regulator of claim 12, wherein the bias current in the second feedback loop is proportional to the bias current in the first feedback loop.

14. The voltage regulator of claim 12, wherein the second feedback loop comprises:

a first transistor and a second transistor, wherein the gates of the first and second transistors are connected to the output of the error amplifier;

a third transistor biasing the current in the first transistor; and

a fourth transistor biasing the current in the second transistor;

wherein the source of the first transistor is connected to the second feedback loop; and

wherein the gate of the third transistor is connected to the gate of the fourth transistor.

15. The voltage regulator of claim 12, wherein the first feedback loop is configured substantially similar to the second feedback loop.

16. The voltage regulator of claim 9, wherein the input stage comprises a differential amplifier, the differential amplifier comprising:

a first feedback loop, wherein the reference input is connected to the first feedback loop;

a second feedback loop, wherein the output of the error amplifier is connected to the second feedback loop; and

a current biasing transistor that biases the current through the first feedback loop and the second feedback loop;

wherein when the output load of the voltage regulator increases, the output voltage of the error amplifier drops and the bias current in the first feedback loop increases.

18. The voltage regulator of claim 9 and further comprising a capacitor connected between the gate of the pass transistor and ground.

19. The voltage regulator of claim 9, wherein the closed-loop bandwidth of the error amplifier is below 20 kHz.

17. The voltage regulator of claim 17 and further comprising a current selector connected to the differential amplifier.

20. A voltage regulator comprising:

a pass transistor, wherein the drain of the pass transistor is connectable to a voltage source and wherein the source of the pass transistor is connected to the output of the voltage regulator; and

an error amplifier comprising;

a reference input connected to a reference voltage source;

an output, the output being connected to the gate of the pass transistor;

a differential amplifier having a first transistor and a second transistor, the gate of the first transistor being connected to the reference input, the gate of the second transistor being connected to the source of the pass transistor, and the drain of the second transistor being connected to the output of the error amplifier; and

a current mirror connected to the first transistor and the second transistor.