INTEGRATED STANDARD-COMPLIANT DATA ACQUISITION DEVICE

• US 20150015267A1
• Filed: 01/16/2013
• Published: 01/15/2015
• Est. Priority Date: 01/16/2012
• Status: Active Grant

• Current Assignee: Maxim Integrated Products, Inc. (Analog Devices, Inc.)
• Original Assignee: Maxim Integrated Products, Inc. (Analog Devices, Inc.)
• Inventors: Mueller, Bryan A., Wheeler, Erik S., Plagens, Mark R., Mader, Urs
• Granted Patent: US 9,716,520 B2
• Time in Patent Office: Days
• US Class Current: 324/426
• CPC Class Codes: H01M 10/4207 for several batteries or cells simultaneously or sequentially
• CPC Class Codes: H01M 10/482 for several batteries or cells simultaneously or sequentially
• CPC Class Codes: H01M 2010/4271 Battery management systems including electronic circuits, e.g. control of current or voltage to keep battery in healthy state, cell balancing
• CPC Class Codes: H01M 2220/20 Batteries in motive systems, e.g. vehicle, ship, plane
• CPC Class Codes: H02J 7/0047 with monitoring or indicating devices or circuits
• CPC Class Codes: H04B 1/123 using adaptive balancing or compensation means adaptive filter circuits and algorithms H03H
• CPC Class Codes: H04B 15/005 Reducing noise, e.g. humm, from the supply
• CPC Class Codes: H04L 25/4904 using self-synchronising codes, e.g. split-phase codes
• CPC Class Codes: Y02E 60/10 Energy storage using batteries
• CPC Class Codes: Y02T 10/70 Energy storage systems for electromobility, e.g. batteries

Abstract

An integrated standard-compliant data acquisition device includes an electrically insulating package including a plurality of conductive leads and an integrated circuit (IC) disposed within the electrically insulating package and electrically coupled to at least some of the plurality of conductive leads. The IC includes a first multiplexer (MUX), a second MUX, a third MUX, an analog-to-digital converter (ADC), a plurality of registers, a fourth MUX, control logic, and communication circuitry. In operation, a first circuit value under a first condition can be determined and stored, a second circuit value under a second condition can be determined and stored, and the decision as to whether there is a fault condition can be mad by comparing the first circuit value and the second circuit value.

Claims

1. An integrated standard-compliant data acquisition device comprising:

an electrically insulating package including a plurality of conductive leads; and

an integrated circuit (IC) disposed within the electrically insulating package and electrically coupled to at least some of the plurality of conductive leads, the IC including;

(a) a first multiplexer (MUX) having a first plurality of inputs and a first MUX output;

(b) a second MUX having a second plurality of inputs and a second MUX output;

(c) a third MUX having inputs coupled to the first MUX output and the second MUX output and having a third MUX output;

(d) an analog-to-digital converter (ADC) having an analog input coupled to the third MUX output and a digital output;

(e) a plurality of registers;

(f) a fourth MUX having inputs coupled to the digital output of the ADC and to the plurality of registers, and having a fourth MUX output;

(g) control logic coupled to the fourth MUX output and to the plurality of registers; and

(h) communication circuitry coupled to the plurality of registers.

2. An integrated standard-compliant data acquisition device as recited in claim 1 wherein the second plurality of inputs are coupled to a corresponding plurality of balancing switches.

3. An integrated standard-compliant data acquisition device as recited in claim 1 wherein the communication circuitry includes Universal Asynchronous Receiver/Transmitter (UART) circuitry.

4. An integrated standard-compliant data acquisition device as recited in claim 3 wherein the UART circuitry includes a digital upstream stream including a first-in-first-out (FIFO) shift register and error-checking circuitry comparing an input to the FIFO shift and an output of the FIFO shift register.

5. An integrated standard-compliant data acquisition device as recited in claim 2 further comprising a processor communicating with the registers.

6. An integrated standard-compliant data acquisition device as recited in claim 5 wherein the processor is disposed within the electrically insulating package.

7. An integrated standard-compliant data acquisition device as recited in claim 3 further comprising a processor communicating with the registers via the UART circuitry.

8. An integrated standard-compliant data acquisition device as recited in claim 7 further comprising memory coupled to the processor and including code segments for:

reading a first measurement taken under a first condition from the registers;

reading a second measurement taken under a second condition from the registers; and

comparing the first measurement to the second measurement to detect a fault condition.

9. An integrated standard-compliant data acquisition device as recited in claim 7 wherein said memory further includes code segments for determining a type of fault condition.

10. An ISO-26262 compliant battery monitoring system comprising:

a first multiplexer (MUX) having a first plurality of inputs coupled to a plurality of battery cells with a plurality of filter resistors, and a first MUX output;

a second MUX having a second plurality of inputs coupled to the plurality of battery cells with a plurality of balance resistors, and a second MUX output;

a plurality of balancing switches coupled between adjacent pairs of the plurality of balance resistors;

a third MUX having inputs coupled to the first MUX output and the second MUX output and having a third MUX output;

an analog-to-digital converter (ADC) having an analog input coupled to the third MUX output and a digital output; and

a data register coupled to the ADC.

11. An ISO-2626 compliant battery monitoring system as recited in claim 10 further comprising a processor coupled to the data register and memory coupled to the processor and including code segments for:

reading a first measurement taken under a first condition from the data register;

reading a second measurement taken under a second condition from the data register; and

comparing the first measurement and the second measurement to detect a fault condition.

12. An ISO-26262 compliant battery monitoring system as recited in claim 11 wherein the processor is coupled to the data register by a Universal Asynchronous Receiver/Transmitter (UART) circuit.

13. A method for battery monitoring comprising:

determining and storing a first circuit value under a first condition;

determining and storing a second circuit value under a second condition; and

determining whether there is a fault by comparing the first circuit value and the second circuit value.

14. A method for battery monitoring as recited in claim 13 further comprising determining a type of fault when the first circuit value differs from the second circuit value by more than the tolerance level.

15. A method for battery monitoring as recited in claim 14 further comprising balancing cells of a battery based, at least in part, from the first circuit value.