ALL N-TYPE TRANSISTOR INVERTER CIRCUIT

• US 20150015556A1
• Filed: 07/09/2013
• Published: 01/15/2015
• Est. Priority Date: 07/09/2013
• Status: Active Grant

• Current Assignee: Snaptrack Incorporated (Qualcomm, Inc.)
• Original Assignee: Pixtronix, Incorporated (Qualcomm, Inc.)
• Inventors: Pappas, Ilias
• Granted Patent: US 9,214,475 B2
• Time in Patent Office: Days
• US Class Current: 345/211
• CPC Class Codes: G09G 2310/0267 Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays
• CPC Class Codes: G09G 2310/0286 Details of a shift registers arranged for use in a driving circuit
• CPC Class Codes: G09G 2310/0291 Details of output amplifiers or buffers arranged for use in a driving circuit
• CPC Class Codes: G09G 2330/021 Power management, e.g. power saving
• CPC Class Codes: G09G 3/3433 using light modulating elements actuated by an electric field and being other than liquid crystal devices and electrochromic devices using liquid crystal devices G09G3/36; using electrochromic devices G09G3/38
• CPC Class Codes: G11C 19/28 using semiconductor elements G11C19/14, G11C19/36 take precedence
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 27/1255 integrated with passive devices, e.g. auxiliary capacitors
• CPC Class Codes: H03K 19/01714 by bootstrapping, i.e. by positive feed-back
• CPC Class Codes: H03K 19/09441 of the same canal type
• CPC Class Codes: H03K 19/20 characterised by logic function, e.g. AND, OR, NOR, NOT circuits H03K19/003 - H03K19/01 take precedence

Abstract

This disclosure provides systems, methods and apparatus for an all n-type transistor inverter circuit. A circuit can include an input thin film transistor (TFT), a pull-down TFT, a discharge TFT, a first pull-up TFT, a second pull-up TFT, and a floating capacitor. The circuit also can include first and second low-voltage voltage sources and first and second high-voltage voltage sources. The TFTs, the capacitor, and the voltage sources can be coupled such that an output of the circuit is the logical opposite of an input of the circuit. In some implementations, the circuit can exhibit zero DC current in both logic states and can output voltages substantially equal to the voltage output by the first low-voltage voltage source and the second high-voltage voltage source. In some implementations, the circuit can be used to construct D flip-flops, buffers, and controllers for an active matrix electronic display.

Claims

1. An all n-type thin film transistor (TFT) circuit, comprising:

a first inverter including;

an input voltage interconnect;

an input TFT coupled at its gate to the input voltage interconnect and to a first low voltage source at its source;

a pull-down TFT coupled to the input voltage interconnect at its gate and a second low voltage source at its source;

a discharge TFT coupled to the input voltage interconnect at its gate and a third low voltage source at its source;

a first pull-up TFT coupled from its source to the drain of the pull-down TFT and a first terminal of a capacitor, from its gate to the drain of the input TFT and a second terminal of the capacitor, and from its drain to a first high voltage source;

a second pull-up TFT coupled from its source to the drain of the discharge TFT, from its gate to the source of the first pull-up transistor and to the first terminal of a first capacitor and the drain of the pull-down TFT, and from its drain to a second high voltage source; and

an output voltage interconnect coupled to a node between the second pull-up TFT and the discharge TFT.

2. The circuit of claim 1, wherein the second low voltage source outputs a voltage that is more negative than a voltage output by first low voltage source.

3. The circuit of claim 1, wherein the first low voltage source is a ground.

4. The circuit of claim 1, wherein the first high voltage source outputs a voltage that is more positive than a voltage output by the second high voltage source.

5. The circuit of claim 1, wherein the first, second, and third low voltage sources and the first and second high voltage sources are DC voltage sources.

6. The circuit of claim 1, wherein the input TFT, the pull-down TFT, the discharge TFT, and the first and second pull-up TFTs are configured such that the voltage on the output voltage interconnect is the logical opposite of the voltage on the input voltage interconnect.

7. The circuit of claim 1, wherein the capacitor is a floating capacitor.

8. The circuit of claim 1, wherein the absolute value of the difference between a logical low input voltage and the voltage output by the second low voltage source is less than the threshold voltage of the first pull-up TFT.

9. The circuit of claim 8, wherein the logical low input voltage is equal to about the voltage output by the first low voltage source and the high input voltage is equal to the voltage output by the second high voltage source.

10. The circuit of claim 1, wherein at least one of the input TFT, the pull-down TFT, the discharge TFT, the first pull-up TFT and the second pull-up TFT include a channel formed from a conductive oxide.

11. The circuit of claim 1, wherein the voltage output by the first low voltage source is about equal to the voltage output by the third low voltage source.

12. The circuit of claim 1, further comprising a second inverter, wherein the output voltage interconnect of the first inverter is electrically coupled to an input voltage interconnect of the second inverter such that the first and second inverters together operate as a buffer.

13. The circuit of claim 1, further comprising:

a sixth TFT coupled at its gate to a trigger signal, at its drain to a data input interconnect, and at its source to the input voltage interconnect of the first inverter;

a second inverter coupled at its input voltage interconnect to the output voltage interconnect of the first inverter, and at its output voltage interconnect to the input voltage interconnect of the first inverter;

a seventh transistor coupled at its gate to an inverted trigger signal and at its drain to the output voltage interconnect of the first inverter circuit;

a third inverter coupled at its input voltage interconnect to the source of the seventh transistor and the output voltage interconnect of a fourth inverter, and at its output voltage interconnect to the input voltage interconnect of the fourth inverter, wherein the first inverter, the second inverter, the third inverter, the fourth inverter, the sixth transistor, and the seventh transistor form a D flip-flop.

14. The circuit of claim 1, further comprising:

a display;

a processor that is configured to communicate with the display, the processor being configured to process image data; and

a memory device that is configured to communicate with the processor.

15. The circuit of claim 14, further comprising:

a driver circuit configured to send at least one signal to the display; and

a controller configured to send at least a portion of the image data to the driver circuit.

16. The circuit of claim 14, further comprising:

an image source module configured to send the image data to the processor, wherein the image source module comprises at least one of a receiver, transceiver, and transmitter; and

an input device configured to receive input data and to communicate the input data to the processor.

17. An apparatus for controlling an electronic display, comprising:

a plurality of D flip-flops each coupled in series to a respective buffer circuit to form a plurality of row drivers, wherein the plurality of D flip-flops and the respective buffer circuits are formed from all n-type thin film transistors (TFTs);

a trigger signal interconnect coupled in parallel to each of the D flip-flops for transmitting a trigger signal, wherein the output of each D flip-flop is further coupled to the input of a subsequent D flip-flop and the input to the row driver corresponding to a first row of the electronic display is coupled to an independently controlled input, such that the outputs of the buffer circuits are enabled sequentially during successive cycles of the trigger signal in response to a logical high voltage being applied at the independently controlled input; and

a control matrix including a plurality of scan-line interconnects, each scan-line interconnect coupled to a respective buffer circuit and a plurality of display elements arranged substantially in a row.

18. The apparatus of claim 17, further comprising:

a substrate, wherein TFTs forming the D flip-flops, the buffer circuits, and the control matrix are fabricated on the substrate.

19. The apparatus of claim 17, further comprising:

a controller for outputting the independently controlled input, wherein the independently controlled input initiates a display addressing process.

20. The apparatus of claim 19, further comprising:

a data driver for sequentially outputting data voltages to display elements in rows enabled by corresponding scan-line interconnects, wherein the controller outputs signals to synchronize the outputs of the data driver and the buffer circuits.