ARRAY SUBSTRATE, METHOD OF DISCONNECTION INSPECTING GATE LEAD WIRE AND SOURCE LEAD WIRE IN THE ARRAY SUBSTRATE, METHOD OF INSPECTING THE ARRAY SUBSTRATE, AND LIQUID CRYSTAL DISPLAY DEVICE

• US 20150015820A1
• Filed: 07/08/2014
• Published: 01/15/2015
• Est. Priority Date: 07/12/2013
• Status: Active Grant

• Current Assignee: Trivale Technologies, LLC (Vector Capital Corporation)
• Original Assignee: Mitsubishi Electric Corporation
• Inventors: MURAKAMI, Katsuaki, MASUTANI, Yuichi
• Granted Patent: US 9,298,055 B2
• Time in Patent Office: Days
• US Class Current: 349/42
• CPC Class Codes: G02F 1/1309 Repairing; Testing
• CPC Class Codes: G02F 1/1345 Conductors connecting electrodes to cell terminals
• CPC Class Codes: G02F 1/136254 Checking; Testing
• CPC Class Codes: G02F 1/136286 Wiring, e.g. gate line, drain line
• CPC Class Codes: G09G 3/006 Electronic inspection or testing of displays and display drivers, e.g. of LED or LCD displays testing individual LED's G01R31/2635; testing lamps G01R31/44; testing of optical features of LCD displays G02F1/1309
• CPC Class Codes: G09G 3/3648 using an active matrix G09G3/367 - G09G3/3696 take precedence

Abstract

An array substrate has a plurality of gate signal lines, a plurality of source signal lines orthogonal to the plurality of gate signal lines, a plurality of gate-driver mounting terminals, a plurality of source-driver mounting terminals, a plurality of gate-side array inspection terminals connected to the gate signal lines, a plurality of source-side array inspection terminals connected to the source signal lines, a plurality of gate lead wire disconnection inspection circuits connected between the plurality of gate-driver mounting terminals and a common terminal for a gate lead wire disconnection inspection, and a plurality of source lead wire disconnection inspection circuits connected between the plurality of source-driver mounting terminals and a common terminal for a source lead wire disconnection inspection.

Claims

1. An array substrate comprising:

a plurality of gate signal lines extending in parallel at equal intervals;

a plurality of source signal lines orthogonal to said plurality of gate signal lines and extending in parallel at equal intervals;

a plurality of gate-driver mounting terminals connected to said plurality of gate signal lines via gate lead wires;

a plurality of source-driver mounting terminals connected to said plurality of source signal lines via source lead wires;

a plurality of gate-side array inspection terminals connected to said plurality of gate signal lines;

a plurality of source-side array inspection terminals connected to said plurality of source signal lines;

a common terminal for a gate lead wire disconnection inspection;

a common terminal for a source lead wire disconnection inspection;

a plurality of gate lead wire disconnection inspection circuits connected between said plurality of gate-driver mounting terminals and said common terminal for a gate lead wire disconnection inspection; and

a plurality of source lead wire disconnection inspection circuits connected between said plurality of source-driver mounting terminals and said common terminal for a source lead wire disconnection inspection.

2. The array substrate according to claim 1, wherein an interval of said gate-side array inspection terminals connected to neighboring gate signal lines is wider than an interval of said gate-driver mounting terminals connected to said neighboring gate signal lines, and an interval of said source-side array inspection terminals connected to neighboring source signal lines is wider than an interval of said source-driver mounting terminals connected to said neighboring source signal lines.

3. The array substrate according to claim 1, wherein said gate lead wire disconnection inspection circuit is a gate-side TFT, a common gate-side switch terminal is connected to a gate of the gate-side TFT,

said source lead wire disconnection inspection circuit is a source-side TFT, and a common source-side switch terminal is connected to a gate of the source-side TFT.

4. The array substrate according to claim 1, wherein said gate lead wire disconnection inspection circuit is a resistive element, and

said source lead wire disconnection inspection circuit is a resistive element.

5. The array substrate according to claim 1, wherein said gate lead wire disconnection inspection circuit is a capacitive element, and said source lead wire disconnection inspection circuit is a capacitive element.

6. The array substrate according to claim 1, wherein said gate lead wire disconnection inspection circuit has a TFT and a capacitive element,

the capacitive element is connected between a drain of the TFT and said common terminal for a gate lead wire disconnection inspection,

a gate of the TFT is connected to said gate-driver mounting terminal,

a common gate lead wire disconnection inspection terminal is connected to a source of the TFT,

said source lead wire disconnection inspection circuit has a TFT and a capacitive element,

the capacitive element is connected between the drain of the TFT and said common terminal for a source lead wire disconnection inspection,

a common source lead wire disconnection inspection terminal is connected to the gate of the TFT, and

the source of the TFT is connected to said source-driver mounting terminal.

7. A disconnection inspecting method for said gate lead wire and said source lead wire in the array substrate described in claim 3, comprising:

measuring, via said gate-side array inspection terminal, an amount of current or charges flowing in each of said gate signal lines when said gate-side TFT is turned on in a state where different voltages are applied to said gate-side array inspection terminal and said common terminal for a gate lead wire disconnection inspection; and

measuring, via said source-side array inspection terminal, an amount of current or charges flowing in each of said source signal lines when said source-side TFT is turned on in a state where different voltages are applied to said source-side array inspection terminal and said common terminal for a source lead wire disconnection inspection.

8. A disconnection inspecting method for said gate lead wire and said source lead wire in the array substrate described in claim 4, comprising:

measuring, via said gate-side array inspection terminal, an amount of current or charges flowing in each of said gate signal lines in a state where different voltages are applied to said gate-side array inspection terminal and said common terminal for a gate lead wire disconnection inspection; and

measuring, via said source-side array inspection terminal, an amount of current or charges flowing in each of said source signal lines in a state where different voltages are applied to said source-side array inspection terminal and said common terminal for a source lead wire disconnection inspection.

9. A disconnection inspecting method for said gate lead wire and said source lead wire in the array substrate described in claim 5, comprising:

measuring, via said gate-side array inspection terminal, an amount of charges flowing in each of said gate signal lines in a state where different voltages are applied to said gate-side array inspection terminal and said common terminal for a gate lead wire disconnection inspection; and

measuring, via said source-side array inspection terminal, an amount of charges flowing in each of said source signal lines in a state where different voltages are applied to said source-side array inspection terminal and said common terminal for a source lead wire disconnection inspection.

10. A method of inspecting the array substrate described in claim 6, comprising:

(a) inspecting disconnection in said gate signal line and said source signal line; and

(b) inspecting disconnection in said gate lead wire and said source lead wire,

wherein at the time of performing said (b),

said gate lead wire inspection terminal is regarded as said gate-side array inspection terminal,

said source lead wire inspection terminal is regarded as said source-side array inspection terminal,

common voltage is supplied to said common terminal for a gate lead wire disconnection inspection and said common terminal for a source lead wire disconnection inspection, and

said (b) is performed in the same manner as that for said (a).

11. A liquid crystal display device comprising:

the array substrate according to claim 1;

a gate driver mounted on said gate-driver mounting terminal of said array substrate;

a source driver mounted on said source-driver mounting terminal of said array substrate;

a circuit for driving said gate driver and said source driver;

an opposed substrate disposed so as to face said array substrate;

a liquid crystal held between said array substrate and said opposed substrate; and

a backlight attached to a back side of said array substrate.