PULSE MODE ACTIVE CLAMPING

• US 20150016153A1
• Filed: 07/12/2013
• Published: 01/15/2015
• Est. Priority Date: 07/12/2013
• Status: Active Grant

• Current Assignee: Solantro Semiconductor Corp. (China Electronics Corporation)
• Original Assignee: Solantro Semiconductor Corp. (China Electronics Corporation)
• Inventors: Orr, Raymond Kenneth, Scarlatescu, Gabriel, Lipan, Tudor
• Granted Patent: US 9,077,254 B2
• Time in Patent Office: Days
• US Class Current: 363/21.04
• CPC Class Codes: H02M 3/33538 of the forward type H02M3/3353, H02M3/33569 take precedence
• CPC Class Codes: Y02B 70/10 Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

Abstract

An active clamp circuit includes a clamp capacitance and a clamp switch coupled in a circuit path, and a diode coupled across the clamp switch.

Claims

1. An apparatus comprising:

an active clamp circuit, the active clamp circuit comprising a clamp capacitance, a diode, and a clamp switch, the clamp capacitance and the clamp switch being coupled in a circuit path, and the diode being coupled across the clamp switch;

a power converter coupled to the active clamp circuit, the power converter comprising a storage inductance coupled in a circuit path with a converter switch; and

a controller, operatively coupled to the clamp switch and the converter switch, to close the clamp switch during a non-conduction phase of the converter switch in a converter switching cycle to cause the clamp capacitance to be discharged into the storage inductance exclusively through the clamp switch, and to subsequently open the clamp switch during the non-conduction phase of the converter switch to cause the clamp capacitance to be charged from the storage inductance exclusively through the diode during a non-conduction phase of the converter switch in a next converter switching cycle.

2. The apparatus of claim 1, wherein the controller is configured to open the clamp switch during the discharge of the clamp capacitance to reduce voltage across the converter switch.

3. The apparatus of claim 1, the circuit path of the power converter being coupled across terminals of an input power source, the circuit path of the active clamp circuit being coupled between (i) a node in the circuit path of the power converter between the storage inductance and the converter switch and (ii) one of the terminals of the input power source.

4. The apparatus of claim 3, the controller being configured to determine timing of a voltage maximum at the node, and to close the clamp switch at the voltage maximum.

5. The apparatus of claim 3, the controller being configured to close the clamp switch for a clamp switch ON time during the non-conduction phase of the converter switch in the converter switching cycle, to open the clamp switch at an end of the clamp switch ON time, to analyze a waveform of the voltage at the node until the converter switch is closed in the next converter switching cycle, and to control a value of the clamp switch ON time for the next converter switching cycle based on the analysis.

6. The apparatus of claim 5, the controller being configured to analyze the waveform of the voltage at the node to determine a value of the node voltage minimum, and to control the value of the clamp switch ON time based on a voltage difference between the determined value of the voltage minimum and a target minimum.

7. The apparatus of claim 3, the controller being configured to close the clamp switch for a clamp switch ON time during the non-conduction phase of the converter switch in the converter switching cycle, to open the clamp switch at an end of the clamp switch ON time, to determine a time interval between the opening of the clamp switch and a time at which voltage at the node reaches a preset voltage, and to control a value of the clamp switch ON time for the next converter switching cycle based on a time difference between the determined time interval and a time interval value which corresponds to a voltage minimum of zero at the node.

8. The apparatus of claim 3, the controller being configured to close the clamp switch at a delay time after the converter switch is opened in the converter switching cycle, to open the clamp switch at an end of the clamp switch ON time during which the clamp switch is closed, to analyze a waveform of the voltage at the node until the converter switch is closed in the next converter switching cycle, and to control a value of the delay time for the next converter switching cycle based on the analysis.

9. The apparatus of claim 8, the controller being configured to analyze the waveform of the voltage at the node to determine a value of a node voltage minimum, and to control the value of the delay time based on a voltage difference between the determined value of the node voltage minimum and a target value.

10. The apparatus of claim 5, the controller being configured to analyze the waveform of the voltage at the node to determine energy stored in the storage inductance, and to control the value of the clamp switch ON time based on an energy difference between the stored energy and a target energy.

11. The apparatus of claim 3,

the clamp switch comprising a PMOS power Metal Oxide Semiconductor Field Effect Transistor (MOSFET), the diode comprising an intrinsic diode formed between a source and a body of the PMOS power MOSFET,

the circuit path of the active clamp circuit being coupled to the node,

the active clamp circuit further comprising a second capacitance coupling the circuit path of the active clamp circuit to the one of the terminals of the input power source,

the controller comprising a voltage supply to supply a node between the second capacitance and the circuit path of the active clamp circuit.

12. A method comprising:

controlling a converter switch of a power converter to provide a conduction phase and a non-conduction phase during converter switching cycles, the power converter comprising a storage inductance coupled in a circuit path with the converter switch;

controlling a clamp switch of an active clamp circuit, the active clamp circuit comprising a clamp capacitance, a diode, and the clamp switch, the clamp capacitance and the clamp switch being coupled in a circuit path, and the diode being coupled across the clamp switch,

controlling the clamp switch comprising closing the clamp switch during the non-conduction phase of the converter switch in a converter switching cycle to cause the clamp capacitance to be discharged into the storage inductance exclusively through the clamp switch, and subsequently opening the clamp switch during the non-conduction phase of the converter switch to cause the clamp capacitance to be charged from the storage inductance exclusively through the diode during the non-conduction phase of the converter switch in next converter switching cycle.

13. The method of claim 12, further comprising:

opening the clamp switch during the discharge of the clamp capacitance to reduce voltage across the converter switch.

14. The method of claim 12, the circuit path of the power converter being coupled across terminals of an input power source, the circuit path of the active clamp circuit being coupled between (i) a node in the circuit path of the power converter between the storage inductance and the converter switch and (ii) one of the terminals of the input power source, the method further comprising:

determining timing of a voltage maximum at the node,

closing the clamp switch comprising closing the clamp switch at the voltage maximum.

15. The method of claim 12, the circuit path of the power converter being coupled across terminals of an input power source, the circuit path of the active clamp circuit being coupled between (i) a node in the circuit path of the power converter between the storage inductance and the converter switch and (ii) one of the terminals of the input power source,

closing the clamp switch comprising closing the clamp switch for a clamp switch ON time during the non-conduction phase of the converter switch in the converter switching cycle,

opening the clamp switch comprising opening the clamp switch at an end of the clamp switch ON time,

the method further comprising:

analyzing a waveform of the voltage at the node until the converter switch is closed in the next converter switching cycle; and

controlling a value of the clamp switch ON time for the next converter switching cycle based on the analysis.

16. The method of claim 15, the analyzing comprising determining a value of the node voltage minimum;

controlling a value of the clamp switch ON time comprising controlling the value of the clamp switch ON time based on a voltage difference between the determined value of the voltage minimum and a target minimum.

17. The method of claim 12, the circuit path of the power converter being coupled across terminals of an input power source, the circuit path of the active clamp circuit being coupled between (i) a node in the circuit path of the power converter between the storage inductance and the converter switch and (ii) one of the terminals of the input power source,

closing the clamp switch comprising closing the clamp switch for a clamp switch ON time during the non-conduction phase of the converter switch in the converter switching cycle,

opening the clamp switch comprising opening the clamp switch at an end of the clamp switch ON time,

the method further comprising:

determining a time interval between the opening of the clamp switch and a time at which voltage at the node reaches a preset voltage;

controlling a value of the clamp switch ON time for the next converter switching cycle based on a time difference between the determined time interval and a time interval value which corresponds to a voltage minimum of zero at the node.

18. The method of claim 12, the circuit path of the power converter being coupled across terminals of an input power source, the circuit path of the active clamp circuit being coupled between (i) a node in the circuit path of the power converter between the storage inductance and the converter switch and (ii) one of the terminals of the input power source,

closing the clamp switch comprising closing the clamp switch at a delay time after the converter switch is opened in the converter switching cycle,

opening the clamp switch comprising opening the clamp switch at and end of a clamp switch ON time during which the clamp switch is closed,

the method further comprising:

analyzing a waveform of the voltage at the node until the converter switch is closed in the next converter switching cycle; and

controlling a value of the delay time for the next converter switching cycle based on the analysis.

19. The method of claim 18, the analyzing comprising determining a value of the node voltage minimum;

controlling a value of the delay time comprising controlling the value of the delay time based on a voltage difference between the determined value of the node voltage minimum and a target value.

20. The method of claim 15, the analyzing comprising determining energy stored in the storage inductance;

controlling a value of the clamp switch ON time comprising controlling the value of the clamp switch ON time based on an energy difference between the stored energy and a target energy.

21. A non-transitory machine-readable medium storing instructions which, when executed, perform the method of claim 12.