SHIFT REGISTER UNIT, DISPLAY PANEL AND DISPLAY DEVICE

• US 20150016584A1
• Filed: 03/26/2014
• Published: 01/15/2015
• Est. Priority Date: 07/11/2013
• Status: Abandoned Application

• Current Assignee: Shanghai AVIC Optoelectronics Company Limited (Tianma Microelectronics Company Limited), Tianma Microelectronics Company Limited
• Original Assignee: Shanghai AVIC Optoelectronics Company Limited (Tianma Microelectronics Company Limited), Tianma Microelectronics Company Limited
• Inventors: XIA, Zhiqiang, DUN, Dongliang
• Application Number:
  US14/226,760
• Publication Number:
  US 20150016584A1
• Time in Patent Office: Days
• US Class Current: 377/68
• CPC Class Codes: G09G 2310/0286 Details of a shift registers arranged for use in a driving circuit
• CPC Class Codes: G09G 3/3266 Details of drivers for scan electrodes
• CPC Class Codes: G11C 19/28 using semiconductor elements G11C19/14, G11C19/36 take precedence
• CPC Class Codes: G11C 27/04 Shift registers

Abstract

A shift register unit, a display panel including the shift register unit and a display device including the display panel are provided. The shift register unit includes a driving module, an output module, a first transistor, and a second transistor. By connecting a second electrode of the first transistor in the shift register unit with an output terminal of the shift register unit, even if a channel width of the second transistor is considerably smaller than a theoretical design value, abnormal output of the shift register unit can be avoided.

Claims

1. A shift register unit comprising a driving module, an output module, a first transistor and a second transistor,

wherein a first port of the driving module receives a positive selection signal, a second port of the driving module receives a first level signal, a third port of the driving module receives a reverse selection signal, a fourth port of the driving module receives a second level signal, a fifth port of the driving module receives a low voltage signal, a sixth port of the driving module is connected with a gate of the first transistor and a first electrode of the second transistor, a seventh port of the driving module is connected with a third port of the output module, an eighth port of the driving module is connected with a first electrode of the first transistor, a gate of the second transistor and a first port of the output module at a pull-up node, a ninth port of the driving module receives a clock blocking signal, a tenth port of the driving module receives a clock signal, a second electrode of the first transistor is connected with the third port of the output module, a second electrode of the second transistor receives the low voltage signal, a second port of the output module receives the clock blocking signal, and the third port of the output module serves as an output terminal of the shift register unit;

the driving module is configured to output the first level signal through the eighth port when the positive selection signal is at a logic high level and the clock blocking signal is at a logic low level, and to output the second level signal through the eighth port when the reverse selection signal is at the logic high level and the clock blocking signal is at the logic low level, and to output the low voltage signal through the seventh port when the clock signal is at the logic high level, and to output the clock blocking signal through the sixth port, and to output the low voltage signal through the seventh port when the first electrode of the second transistor is at the logic high level;

the output module is configured to output the clock blocking signal through the third port of the output module when the pull-up node is at a turn-on level and stops outputting the clock blocking signal when the pull-up node is at a turn-off level;

the first transistor is configured to connect the pull-up node with the output end of the shift register unit when the first electrode of the second transistor is at the logic high level and to disconnect the pull-up node from the output end of the shift register unit when the first electrode of the second transistor is at the logic low level; and

the second transistor is configured to control the first electrode of the second transistor to be the low voltage signal when the pull-up node is at the turn-on level and to be turned off when the pull-up node is at the turn-off level.

2. The shift register unit of claim 1, wherein the driving module comprises a first driving cell, a second driving cell and a third driving cell, wherein:

a first port of the first driving cell is connected with the first port of the driving module, a second port of the first driving cell is connected with the second port of the driving module, a third port of the first driving cell and a third port of the second driving cell are connected with the eighth port of the driving module, a first port of the second driving cell is connected with the third port of the driving module, a second port of the second driving cell is connected with the fourth port of the driving module, a first port of the third driving cell is connected with the ninth port of the driving module, a second port of the third driving cell is connected with the tenth port of the driving module, a third port of the third driving cell is connected with the seventh port of the driving module, a fourth port of the third driving cell is connected with the fifth port of the driving module, and a fifth port of the third driving cell is connected with the sixth port of the driving module;

the first driving cell is configured to output the first level signal through the third port of the first driving cell when the positive selection signal is at the logic high level;

the second driving cell is configured to output the second level signal through the third port of the second driving cell when the reverse selection signal is at the logic high level; and

the third driving cell is configured to output the low voltage signal through the third port of the third driving cell when the clock signal is at the logic high level and to output the clock blocking signal through the fifth port of the third driving cell, and to output the low voltage signal through the third port of the third driving cell when the first electrode of the second transistor is at the logic high level.

3. The shift register unit of claim 2, wherein the first driving cell comprises a third transistor, wherein:

a gate of the third transistor is connected with the first port of the first driving cell, a first electrode of the third transistor is connected with the second port of the first driving cell, and a second electrode of the third transistor is connected with the third port of the first driving cell; and

the third transistor is configured to be turned on when the positive selection signal is at the logic high level 1 and to be turned off when the positive selection signal is at the logic low level.

4. The shift register unit of claim 2, wherein the second driving cell comprises a fourth transistor, wherein:

a gate of the fourth transistor is connected with the first port of the second driving cell, a first electrode of the fourth transistor is connected with the second port of the second driving cell, and a second electrode of the fourth transistor is connected with the third port of the second driving cell; and

the fourth transistor is configured to be turned on when the reverse selection signal is at the logic high level and to be turned off when the reverse selection signal is at the logic low level.

5. The shift register unit of claim 2, wherein the third driving cell comprises a first capacitor, a fifth transistor and a sixth transistor, wherein:

one terminal of the first capacitor is connected with the first port of the third driving cell, the other terminal of the first capacitor and a gate of the fifth transistor are connected with the fifth port of the third driving cell, a first electrode of the fifth transistor and a first electrode of the sixth transistor are connected with the third port of the third driving cell, a second electrode of the fifth transistor and a second electrode of the sixth transistor are connected with the fourth port of the third driving cell, and a gate of the sixth transistor is connected with the second port of the third driving cell;

the first capacitor is configured to couple the received clock blocking signal to the first electrode of the second transistor;

the fifth transistor is configured to be turned on when the first electrode of the second transistor is at the logic high level and to be turned off when the first electrode of the second transistor is at the logic low level; and

the sixth transistor is configured to be turned on when the clock signal is at the logic high level and to be turned off when the clock signal is at the logic low level.

6. The shift register unit of claim 1, wherein the output module comprises a second capacitor and a seventh transistor,

one terminal of the second capacitor and a gate of the seventh transistor are connected with the first port of the output module, the other terminal of the second capacitor and a second electrode of the seventh transistor are connected with the third port of the output module, and a first electrode of the seventh transistor is connected with the second port of the output module;

the second capacitor is configured to store a signal of the pull-up node; and

the seventh transistor is configured to be turned on when the pull-up node is at the logic high level and to be turned off when the pull-up node is at the logic low level.

7. The shift register unit of claim 1, further comprising a first reset module, wherein a first port of the first reset module receives a reset signal, and a second port of the first reset module is connected with the first electrode of the second transistor;

and

the first reset module is configured to, when the reset signal is at the logic high level, output the high level signal through the second port of the first reset module.

8. The shift register unit of claim 7, wherein the first reset module comprises an eighth transistor having a gate and a first electrode connected with the first port of the first reset module, and a second electrode connected with the second port of the first reset module;

and

the eighth transistor is configured to be turned on when the reset signal is at the logic high level and to be turned off when the reset signal is at the logic low level.

9. The shift register unit of claim 1, further comprising a second reset module, wherein a first port of the second reset module is connected with the pull-up node, a second port of the second reset module receives the low voltage signal, a third port of the second reset module is connected with the output terminal of the shift register unit, and a fourth port of the second reset module receives a reset signal;

and

the second reset module is configured to output the low voltage signal through the first port and the third port of the second reset module respectively when the reset signal is at the logic high level.

10. The shift register unit of claim 9, wherein the second reset module comprises a ninth transistor and a tenth transistor,

gates of the respective ninth transistor and the tenth transistor are connected with the fourth port of the second reset module, a first electrode of the ninth transistor is connected with the first port of the second reset module, second electrodes of the respective ninth transistor and the tenth transistor are connected with the second port of the second reset module, and a first electrode of the tenth transistor is connected with the third port of the second reset module;

the ninth transistor is configured to be turned on when the reset signal is at the logic high level and to be turned off when the reset signal is at the logic low level; and

the tenth transistor is configured to be turned on when the reset signal is at the logic high level signal and to be turned off when the reset signal is at the logic low level.

11. A display panel comprising a shift register unit comprising a driving module, an output module, a first transistor and a second transistor, wherein:

a first port of the driving module receives a positive selection signal, a second port of the driving module receives a first level signal, a third port of the driving module receives a reverse selection signal, a fourth port of the driving module receives a second level signal, a fifth port of the driving module receives a low voltage signal, a sixth port of the driving module is connected with a gate of the first transistor and a first electrode of the second transistor, a seventh port of the driving module is connected with a third port of the output module, an eighth port of the driving module is connected with a first electrode of the first transistor, a gate of the second transistor and a first port of the output module at a connecting node being a pull-up node, a ninth port of the driving module receives a clock blocking signal, a tenth port of the driving module receives a clock signal, a second electrode of the first transistor is connected with the third port of the output module, a second electrode of the second transistor receives the low voltage signal, a second port of the output module receives the clock blocking signal, and the third port of the output module serves as an output terminal of the shift register unit;

the driving module is configured to output the first level signal through the eighth port when the positive selection signal is a logic high level and the clock blocking signal is at a logic low level, and to output the second level signal through the eighth port when the reverse selection signal is at the logic high level signal and the clock blocking signal is at the logic low level, and to output the low voltage signal through the seventh port when the clock signal is at the logic high level signal, and to output the clock blocking signal through the sixth port, and to output the low voltage signal through the seventh port when the first electrode of the second transistor is at the logic high level;

the output module is configured to output the clock blocking signal through the third port of the output module when the pull-up node is at a turn-on level, and stops outputting the clock blocking signal when the pull-up node is at a turn-off level;

the first transistor is configured to connect the pull-up node with the output terminal of the shift register unit when a signal of the first electrode of the second transistor is a high level signal, and to disconnect the pull-up node from the output terminal of the shift register unit when a potential of the first electrode of the second transistor is low; and

the second transistor is configured to control a signal of the first electrode of the second transistor to be the low voltage signal when the pull-up node is at the turn-on level, and to be turned off when the pull-up node is at the turn-off level.

12. The display panel of claim 11, wherein the driving module comprises a first driving cell, a second driving cell and a third driving cell,

a first port of the first driving cell is connected with the first port of the driving module, a second port of the first driving cell is connected with the second port of the driving module, a third port of the first driving cell and a third port of the second driving cell are connected with the eighth port of the driving module, a first port of the second driving cell is connected with the third port of the driving module, a second port of the second driving cell is connected with the fourth port of the driving module, a first port of the third driving cell is connected with the ninth port of the driving module, a second port of the third driving cell is connected with the tenth port of the driving module, a third port of the third driving cell is connected with the seventh port of the driving module, a fourth port of the third driving cell is connected with the fifth port of the driving module, and a fifth port of the third driving cell is connected with the sixth port of the driving module;

the first driving cell is configured to output the first level signal through the third port of the first driving cell when the positive selection signal is at the logic high level;

the second driving cell is configured to output the second level signal through the third port of the second driving cell when the reverse selection signal is at the logic high level; and

the third driving cell is configured to output the low voltage signal through the third port of the third driving cell when the clock signal is at the logic high level, and to output the clock blocking signal through the fifth port of the third driving cell, and to output the low voltage signal through the third port of the third driving cell when the first electrode of the second transistor is at the logic high level.

13. The display panel of claim 12, wherein the first driving cell comprises a third transistor,

a gate of the third transistor is connected with the first port of the first driving cell, a first electrode of the third transistor is connected with the second port of the first driving cell, and a second electrode of the third transistor is connected with the third port of the first driving cell;

and

the third transistor is configured to be turned on when the positive selection signal is at the logic high level and to be turned off when the positive selection signal is at the logic low level.

14. The display panel of claim 12, wherein the second driving cell comprises a fourth transistor,

a gate of the fourth transistor is connected with the first port of the second driving cell, a first electrode of the fourth transistor is connected with the second port of the second driving cell, and a second electrode of the fourth transistor is connected with the third port of the second driving cell;

and

the fourth transistor is configured to be turned on when the reverse selection signal is at the logic high level and to be turned off when the reverse selection signal is at the logic low level.

15. The display panel of claim 12, wherein the third driving cell comprises a first capacitor, a fifth transistor and a sixth transistor,

one terminal of the first capacitor is connected with the first port of the third driving cell, the other terminal of the first capacitor and a gate of the fifth transistor are connected with the fifth port of the third driving cell, a first electrode of the fifth transistor and a first electrode of the sixth transistor are connected with the third port of the third driving cell, a second electrode of the fifth transistor and a second electrode of the sixth transistor are connected with the fourth port of the third driving cell, and a gate of the sixth transistor is connected with the second port of the third driving cell;

the first capacitor is configured to couple the received clock blocking signal to the first electrode of the second transistor;

the fifth transistor is configured to be turned on when the first electrode of the second transistor is at the logic high level and to be turned off when the first electrode of the second transistor is at the logic low level; and

the sixth transistor is configured to be turned on when the clock signal is at the logic high level and to be turned off when the clock signal is at the logic low level.

16. The display panel of claim 11, wherein the output module comprises a second capacitor and a seventh transistor,

one terminal of the second capacitor and a gate of the seventh transistor are connected with the first port of the output module, the other terminal of the second capacitor and a second electrode of the seventh transistor are connected with the third port of the output module, and a first electrode of the seventh transistor is connected with the second port of the output module;

the second capacitor is configured to store a signal of the pull-up node; and

the seventh transistor is configured to be turned on when the pull-up node is at the turn-on level and to be turned off when the pull-up node is at the turn-off level.

17. The display panel of claim 11, wherein the shift register unit further comprises a first reset module, a first port of the first reset module receives a reset signal, and a second port of the first reset module is connected with the first electrode of the second transistor;

and

the first reset module is configured to, when the reset signal is at the logic high level, output the high level signal through the second port of the first reset module.

18. The display panel of claim 17, wherein the first reset module comprises an eighth transistor including a gate and a first electrode connected with the first port of the first reset module, and a second electrode connected with the second port of the first reset module;

and

the eighth transistor is configured to be turned on when the reset signal is at the logic high level and to be turned off when the reset signal is at the logic low level.

19. The display panel of claim 11, wherein the shift register unit further comprises a second reset module having a first port connected with the pull-up node, a second port for receiving the low voltage signal, a third port connected with the output terminal of the shift register unit, and a fourth port for receiving a reset signal;

and

the second reset module is configured to output the low voltage signal through the first port and the third port of the second reset module, respectively, when the reset signal is at the logic high level.

20. The display panel of claim 19, wherein the second reset module comprises a ninth transistor and a tenth transistor,

gates of the respective ninth transistor and tenth transistor are connected with the fourth port of the second reset module, a first electrode of the ninth transistor is connected with the first port of the second reset module, second electrodes of the respective ninth transistor and tenth transistor are connected with the second port of the second reset module, and a first electrode of the tenth transistor is connected with the third port of the second reset module;

the ninth transistor is configured to be turned on when the reset signal is at the logic high level and to be turned off when the reset signal is at the logic low level; and

the tenth transistor is configured to be turned on when the reset signal is at the logic high level and to be turned off when the reset signal is at the logic low level.