ELECTRONIC DEVICE USING GROUP III NITRIDE SEMICONDUCTOR AND ITS FABRICATION METHOD AND AN EPITAXIAL MULTI-LAYER WAFER FOR MAKING IT

• US 20150017789A1
• Filed: 08/14/2014
• Published: 01/15/2015
• Est. Priority Date: 04/07/2006
• Status: Active Grant

• Current Assignee: Seoul Semiconductor Co., Ltd.
• Original Assignee: SixPoint Materials, Inc.
• Inventors: HASHIMOTO, TADAO
• Granted Patent: US 9,349,592 B2
• Time in Patent Office: Days
• US Class Current: 438/503
• CPC Class Codes: C23C 16/303 Nitrides
• CPC Class Codes: H01L 21/02389 Nitrides
• CPC Class Codes: H01L 21/0242 Crystalline insulating materials
• CPC Class Codes: H01L 21/0243 Surface structure
• CPC Class Codes: H01L 21/02458 Nitrides
• CPC Class Codes: H01L 21/0254 Nitrides
• CPC Class Codes: H01L 21/02584 Delta-doping
• CPC Class Codes: H01L 21/0262 Reduction or decomposition of gaseous compounds, e.g. CVD
• CPC Class Codes: H01L 21/02623 Liquid deposition
• CPC Class Codes: H01L 21/02694 Controlling the interface between substrate and epitaxial layer, e.g. by ion implantation followed by annealing
• CPC Class Codes: H01L 29/0646 PN junctions
• CPC Class Codes: H01L 29/0653 adjoining the input or output region of a field-effect device, e.g. the source or drain region
• CPC Class Codes: H01L 29/2003 Nitride compounds
• CPC Class Codes: H01L 29/201 including two or more compounds , e.g. alloys H01L29/2006 takes precedence
• CPC Class Codes: H01L 29/205 in different semiconductor regions , e.g. heterojunctions
• CPC Class Codes: H01L 29/207 further characterised by the doping material H01L29/2006 takes precedence
• CPC Class Codes: H01L 29/32 the imperfections being within the semiconductor body
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/66462 with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
• CPC Class Codes: H01L 29/7784 with delta or planar doped donor layer H01L29/7785 takes precedence
• CPC Class Codes: H01L 29/7828 : without inversion channel, e.g. vertical ACCUFETs, normally-on vertical MISFETs
• CPC Class Codes: H01L 29/8122 : Vertical transistors SIT, PBT H01L29/7722
• CPC Class Codes: H01L 29/8611 : Planar PN junction diodes
• CPC Class Codes: H01L 29/872 : Schottky diodes

Abstract

The present invention discloses an electronic device using a group III nitride substrate fabricated via the ammonothermal method. By utilizing the high-electron concentration of ammonothermally grown substrates having the dislocation density less than 10⁵ cm⁻², combined with a high-purity active layer of Ga_1-x-yAl_xIn_yN (0≦x≦1, 0≦y≦1) grown by a vapor phase method, the device can attain high level of breakdown voltage as well as low on-resistance. To realize a good matching between the ammonothermally grown substrate and the high-purity active layer, a transition layer is optionally introduced. The active layer is thicker than a depletion region created by a device structure in the active layer.

Claims

1. A method of fabricating an electronic device comprising;

(a) growing an active layer of Ga_1-x2-y2Al_x2In_y2N (0≦

x2≦

1, 0≦

y2≦

1) by vapor phase epitaxy on a first side of a substrate of Ga_1-x1-y1Al_x1In_y1N (0≦

x1≦

1, 0≦

y1≦

1) sliced from a bulk crystal of Ga_1-x1-y1Al_x1In_y1N (0≦

x1≦

1, 0≦

y1≦

1) grown in supercritical ammonia;

(b) forming an Ohmic contact on a second side of the substrate;

(c) forming a Schottky contact, metal-insulator-semiconductor structure or p-type semiconductor on the active layer;

wherein

(d) the substrate has a dislocation density of less than 10⁵ cm<sup>−

2</sup>;

(e) the substrate has electron concentration or an oxygen concentration higher than 10¹⁸ cm<sup>−

3</sup>;

(f) the active layer has an electron concentration or an oxygen concentration of less than 10¹⁸ cm<sup>−

3</sup>;

(g) the active layer has a thickness greater than a thickness of the depletion region for any applied voltage within an operation range of the device.

2. A method according to claim 1 wherein the active layer has a sufficiently low concentration of sodium that the active layer contains at least 100 times less sodium than the substrate, and the substrate contains sodium at a concentration greater than 10¹⁶ cm⁻

3.

3. A method according to claim 1 wherein the electron concentration of the active layer is less than 10¹⁶ cm⁻

3.

4. A method according to claim 1 wherein the oxygen concentration of the active layer is less than 10¹⁶ cm⁻

3.

5. A method according to claim 1 wherein step (a) includes growth of a transition layer of Ga_1-x3-y3Al_x3In_y3N (0≦

x3≦

1, 0≦

y3≦

1) between the substrate and the active layer.

6. A method according to claim 5 and further comprising varying an impurity concentration of the transition layer as the transition layer is grown.

7. A method according to claim 5 and further comprising varying composition of the transition layer as the transition layer is grown.

8. A method according to claim 1 further comprising the following two steps before growing the active layer;

(a) forming a dielectric layer on the first side of the substrate; and

(b) forming a hole in the dielectric layer to expose a portion of the first side of the substrate;

and wherein said Schottky contact, metal-insulator-semiconductor structure or p-type semiconductor is formed above the hole in the dielectric layer.

9. A method according to claim 8 wherein the Schottky contact, metal-insulator-semiconductor structure or p-type semiconductor is formed above the hole in the dielectric layer before growing the active layer.

10. A method according to claim 8 wherein the dielectric layer comprises silicon dioxide.

11. A method according to claim 8 wherein the transition layer and/or the active layer is formed using vapor phase epitaxy that deposits said layer'"'"'s material selectively in the hole of the dielectric layer and then laterally.

12. A method according to claim 11 wherein the material deposited laterally extends to an adjacent device on the substrate so that the active layer forms a continuous film.

13. A method according to claim 11 wherein the material deposited laterally does not extend to an adjacent device on the substrate so that the active layer forms a discontinuous film.

14. A method according to claim 1 wherein x1=x2=0 and y1=y2=0.

15. A method according to claim 5 wherein x3=0 and y3=0.

16. A method according to claim 15 wherein x1=x2=0 and y1=y2=0.