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MONOLITHIC THREE DIMENSIONAL (3D) RANDOM ACCESS MEMORY (RAM) ARRAY ARCHITECTURE WITH BITCELL AND LOGIC PARTITIONING

  • US 20150019802A1
  • Filed: 08/28/2013
  • Published: 01/15/2015
  • Est. Priority Date: 07/11/2013
  • Status: Abandoned Application
First Claim
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1. A three dimensional (3D) random access memory (RAM), comprising:

  • a first 3D integrated circuit (IC) (3DIC) tier, comprising;

    a first RAM data bank disposed in the first 3DIC tier;

    a second RAM data bank disposed in the first 3DIC tier;

    a first RAM access logic comprising a first global block control logic disposed between the first RAM data bank disposed in the first 3DIC tier and the second RAM data bank disposed in the first 3DIC tier, the RAM access logic configured to control data access to the first RAM data bank disposed in the first 3DIC tier and the second RAM data bank disposed in the first 3DIC tier;

    a second 3DIC tier, comprising;

    a first RAM data bank disposed in the second 3DIC tier;

    a second RAM data bank disposed in the second 3DIC tier;

    a second RAM access logic comprising a second global block control logic disposed between the first RAM data bank disposed in the second 3DIC tier and the second RAM data bank disposed in the second 3DIC tier, the second RAM access logic configured to control data access to the first RAM data bank disposed in the second 3DIC tier and the second RAM data bank disposed in the second 3DIC tier.

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