MEMORY HIERARCHY USING ROW-BASED COMPRESSION

• US 20150019813A1
• Filed: 07/11/2013
• Published: 01/15/2015
• Est. Priority Date: 07/11/2013
• Status: Active Grant

• Current Assignee: Advanced Micro Devices, Inc.
• Original Assignee: Advanced Micro Devices, Inc.
• Inventors: Loh, Gabriel H., O'Connor, James M.
• Granted Patent: US 9,477,605 B2
• Time in Patent Office: Days
• US Class Current: 711/122
• CPC Class Codes: G06F 12/0866 for peripheral storage systems, e.g. disk cache
• CPC Class Codes: G06F 12/0895 of parts of caches, e.g. directory or tag array
• CPC Class Codes: G06F 2212/1024 Latency reduction
• CPC Class Codes: G06F 2212/1036 Life time enhancement
• CPC Class Codes: G06F 2212/401 Compressed data

Abstract

A system includes a first memory and a device coupleable to the first memory. The device includes a second memory to cache data from the first memory. The second memory includes a plurality of rows, each row including a corresponding set of compressed data blocks of non-uniform sizes and a corresponding set of tag blocks. Each tag block represents a corresponding compressed data block of the row. The device further includes decompression logic to decompress data blocks accessed from the second memory. The device further includes compression logic to compress data blocks to be stored in the second memory.

Claims

1. A system comprising:

a device coupleable to a first memory, the device comprising;

a second memory to cache data from the first memory, the second memory comprising;

a plurality of rows, each row comprising a corresponding set of compressed data blocks of non-uniform sizes and a corresponding set of tag blocks, each tag block representing a corresponding compressed data block of the row; and

decompression logic to decompress data blocks accessed from the second memory.

2. The system of claim 1, wherein the device further comprises:

compression logic to compress data blocks to be stored in the second memory.

3. The system of claim 1, further comprising:

the first memory, wherein the first memory comprises a non-volatile memory; and

wherein the second memory comprises a volatile memory.

4. The system of claim 1, wherein:

the device comprises an integrated circuit (IC) package comprising the second memory and a processor, and

the first memory comprises a memory device external to the IC package.

5. The system of claim 1, wherein each tag block comprises a size indicator for the corresponding compressed data block.

6. The system of claim 1, wherein:

each tag block comprises a size indicator and an address value for the corresponding compressed data block; and

the device further comprises;

control logic to, in response to a memory access request to the device, identify a compressed data block of the set of compressed data blocks as storing requested data based on the address values of the set of tag blocks of the row, identify a location of the compressed data block in the row based on the size indicators of the tag blocks, and access the identified compressed data block from the identified location.

7. The system of claim 6, wherein:

the memory access request comprises a modify request; and

the control logic further is to modify a decompressed version of the compressed data block based on the modify request to generate a modified data block, compress the modified data block to generate a compressed modified data block, store the compressed modified data block to the row as a compressed data block of the set of compressed data blocks, and store a tag block associated with the compressed modified data block to the row as a tag block of the set of tag blocks, the stored tag block comprising a size indicator of the compressed modified data block.

8. The system of claim 7 wherein the control logic comprises:

shuffle/compact logic to shuffle a location of at least one other compressed data block in the row to create a space in the row for the compressed modified data block.

9. The system of claim 6, wherein the control logic further is to provide the accessed compressed data block for storage at the first memory.

10. The system of claim 9, further comprising:

the first memory, wherein the first memory comprises;

decompression logic to decompress the accessed compressed data block to generate a decompressed data block for storage at the first memory.

11. The system of claim 10, wherein the first memory further comprises:

compression logic to compress a data block accessed from the first memory prior to transfer of the data block to the device.

12. A method comprising:

storing, at a row of a first memory, a set of compressed data blocks of non-uniform sizes and a set of tag blocks, each tag block representing a corresponding compressed data block of the row.

13. The method of claim 12, wherein each tag block comprises a size indicator for the corresponding compressed data block.

14. The method of claim 12, wherein:

each tag block comprises a size indicator for the corresponding compressed data block and an address value associated with the compressed data block; and

the method further comprises;

in response to a memory access request to the device;

identifying a compressed data block of the set of compressed data blocks as storing requested data based on the address values of the set of tag blocks of the row;

identifying a location of the compressed data block in the row based on the size indicators of the tag blocks; and

accessing the compressed data block from the identified location.

15. The method of claim 14, further comprising:

decompressing the accessed compressed data block to generate a decompressed data block.

16. The method of claim 15, further comprising:

providing the decompressed data block for storage at a second memory.

17. The method of claim 14, further comprising:

transmitting the accessed compressed data block to a second memory for storage.

18. The method of claim 17, further comprising:

decompressing, at the second memory, the accessed compressed data block to generate a decompressed data block; and

storing the decompressed data block at a memory array of the second memory.

19. The method of claim 17, further comprising:

determining a current offset for a row of the second memory based on a previous offset used to previously store a compressed data block at the row; and

storing the accessed compressed data block at a location of the row based on the current offset.

20. A non-transitory computer readable storage medium embodying a set of executable instructions, the set of executable instructions to manipulate a computer system to perform a portion of a process to fabricate at least part of a device, the device coupleable to a first memory and comprising:

a second memory to cache data from the first memory, the second memory comprising;

a plurality of rows, each row comprising a corresponding set of compressed data blocks of non-uniform sizes and a corresponding set of tag blocks, each tag block representing a corresponding compressed data block of the row; and

decompression logic to decompress data blocks accessed from the second memory.