MEMORY HIERARCHY USING PAGE-BASED COMPRESSION

• US 20150019834A1
• Filed: 07/11/2013
• Published: 01/15/2015
• Est. Priority Date: 07/11/2013
• Status: Active Grant

• Current Assignee: Advanced Micro Devices, Inc.
• Original Assignee: Advanced Micro Devices, Inc.
• Inventors: Loh, Gabriel H., O'Connor, James M.
• Granted Patent: US 11,132,300 B2
• Time in Patent Office: Days
• US Class Current: 711/208
• CPC Class Codes: G06F 12/023 Free address space management
• CPC Class Codes: G06F 12/0868 Data transfer between cache memory and other subsystems, e.g. storage devices or host systems
• CPC Class Codes: G06F 2212/401 Compressed data

Abstract

A system includes a device coupleable to a first memory. The device includes a second memory to cache data from the first memory. The second memory is to store a set of compressed pages of the first memory and a set of page descriptors. Each compressed page includes a set of compressed data blocks. Each page descriptor represents a corresponding page and includes a set of location identifiers that identify the locations of the compressed data blocks of the corresponding page in the second memory. The device further includes compression logic to compress data blocks of a page to be stored to the second memory and decompression logic to decompress compressed data blocks of a page accessed from the second memory.

Claims

1. A system comprising:

a device coupleable to a first memory, the device comprising;

a second memory to cache data from the first memory, wherein the second memory is to store a set of compressed pages of the first memory and a set of page descriptors, each compressed page comprising a set of compressed data blocks, and each page descriptor representing a corresponding page and comprising a set of location identifiers that identify the locations of the compressed data blocks of the corresponding page in the second memory.

2. The system of claim 1, wherein the device further comprises:

compression logic to compress data blocks of a page to be stored to the second memory; and

decompression logic to decompress compressed data blocks of a page accessed from the second memory.

3. The system of claim 1, further comprising:

the first memory, wherein the first memory comprises a non-volatile memory; and

wherein the second memory comprises a volatile memory.

4. The system of claim 1, wherein:

the device comprises an integrated circuit (IC) package comprising the second memory and a processor, and

the first memory comprises a memory device external to the IC package.

5. The system of claim 1, wherein:

each page descriptor includes an address value for the corresponding page; and

the device further comprises;

control logic to, in response to a memory access request to the device, identify a compressed data block of a compressed page stored in the second memory as storing requested data based on the address values of the page descriptors, identify a location of the compressed data block in the second memory based on the location identifiers of a page descriptor associated with the page, and access the compressed data block from the identified location.

6. The system of claim 5, further comprising:

decompression logic to decompress the accessed compressed data block to generate a decompressed data block; and

wherein the control logic further is to provide the decompressed data block for storage at the first memory.

7. The system of claim 5, wherein the control logic further is to provide the accessed compressed data block for storage at the first memory.

8. The system of claim 7, further comprising:

the first memory, wherein the first memory comprises;

decompression logic to decompress the accessed compressed data block to generate a decompressed data block for storage at a corresponding page of the first memory.

9. The system of claim 8, wherein the first memory further comprises:

compression logic to compress a data block of a page accessed from the first memory prior to transfer of the data block to the device.

10. A method comprising:

storing, at a first memory, a set of compressed pages from a second memory and a set of page descriptors, each compressed page comprising a set of compressed data blocks, and each page descriptor representing a corresponding page and comprising a set of location identifiers that identify the locations of the compressed data blocks of the corresponding page in the first memory.

11. The method of claim 10, further comprising:

in response to a memory access request to the device;

identifying a compressed page of the set of compressed pages as storing requested data based on the set of page descriptors;

identifying a location of a compressed data block of the identified compressed page that stores the requested data based on the set of location identifiers of the page descriptor associated with the identified compressed page; and

accessing the compressed data block from the identified location.

12. The method of claim 11, further comprising:

decompressing the accessed compressed data block to generate a decompressed data block.

13. The method of claim 12, further comprising:

providing the decompressed data block for storage at the first memory.

14. The method of claim 11, further comprising:

transmitting the accessed compressed data block to the first memory for storage.

15. The method of claim 14, further comprising:

decompressing, at the first memory, the accessed compressed data block to generate a decompressed data block; and

storing the decompressed data block at the corresponding page of the second memory.

16. The method of claim 10, wherein storing the set of compressed pages comprises:

receiving, at the first memory, a page from the second memory;

compressing the page to generate a set of compressed data blocks;

storing the set of compressed data blocks at the first memory;

generating a page descriptor, the page descriptor comprising location identifiers identifying the locations in the first memory of the compressed data blocks of the set; and

storing the page descriptor to a page descriptor table in the first memory.

17. A non-transitory computer readable storage medium embodying a set of executable instructions, the set of executable instructions to manipulate a computer system to perform a portion of a process to fabricate at least part of a device, the device coupleable to a first memory and comprising:

a second memory to cache data from the first memory, wherein the second memory is to store a set of compressed pages of the first memory and a set of page descriptors, each compressed page comprising a set of compressed data blocks, and each page descriptor representing a corresponding page and comprising a set of location identifiers that identify the locations of the compressed data blocks of the corresponding page in the second memory.

18. The computer readable storage medium of claim 17, wherein the device further comprises:

compression logic to compress data blocks of a page to be stored to the second memory; and

decompression logic to decompress compressed data blocks of a page accessed from the second memory.

19. The computer readable storage medium of claim 17, wherein:

each page descriptor includes an address value for the corresponding page; and

the device further comprises;

control logic to, in response to a memory access request to the device, identify a compressed data block of a compressed page stored in the second memory as storing requested data based on the address values of the page descriptors, identify a location of the compressed data block in the second memory based on the location identifiers of a page descriptor associated with the page, and access the compressed data block from the identified location.

20. The computer readable storage medium of claim 19, wherein the device further comprises:

decompression logic to decompress the accessed compressed data block to generate a decompressed data block; and

wherein the control logic further is to provide the decompressed data block for storage at the first memory.