FAULT BITS SCRAMBLING MEMORY AND METHOD THEREOF
First Claim
1. A fault bits scrambling memory, comprising:
- at least a memory bank, each memory bank comprising a memory module, the memory module comprising a plurality of pages, each page comprising a plurality of memory cells, each memory cell having a physical address;
a scrambling logic unit, receiving a scrambling code and the physical address to generate a mapping address by logical computation, and outputting the mapping address to the memory module so that an external module accesses the data of the memory cell corresponding to the mapping address according to the physical address;
a self-testing unit, detecting faulty memory cells of each page to generate a faulty information; and
a scrambling code generating unit, receiving the faulty information and generating the scrambling code to maintain the number of the faulty memory cells corresponding to the mapping address of the same page is up to a maximum tolerance.
1 Assignment
0 Petitions
Accused Products
Abstract
A fault bits scrambling memory and method thereof relate to a memory including at least one memory bank. The memory bank includes a memory module, a scrambling-logic unit, a self-testing unit and a scrambling code generating unit. The memory module includes a plurality of pages. Each page has a plurality of memory cells, and each memory cell has a physical address. The scrambling logic unit receives a scrambling code and the physical address to generate a mapping address by logical calculation, and outputs the mapping address to the memory module. The self-testing unit detects the faulty memory cells of each page. The scrambling code generating unit is applied to generate the scrambling code to maintain the number of the faulty memory cells corresponding to the mapping address of the same page is up to a maximum tolerance.
4 Citations
9 Claims
-
1. A fault bits scrambling memory, comprising:
-
at least a memory bank, each memory bank comprising a memory module, the memory module comprising a plurality of pages, each page comprising a plurality of memory cells, each memory cell having a physical address; a scrambling logic unit, receiving a scrambling code and the physical address to generate a mapping address by logical computation, and outputting the mapping address to the memory module so that an external module accesses the data of the memory cell corresponding to the mapping address according to the physical address; a self-testing unit, detecting faulty memory cells of each page to generate a faulty information; and a scrambling code generating unit, receiving the faulty information and generating the scrambling code to maintain the number of the faulty memory cells corresponding to the mapping address of the same page is up to a maximum tolerance. - View Dependent Claims (2, 3, 4, 5)
-
-
6. A fault bits scrambling method, applicable to a memory having a plurality of pages, each page comprising a plurality of memory cells, each memory cell having a physical address, the fault bits scrambling method comprising:
-
detecting faulty memory cells of each page to generate a faulty information; generating a scrambling code; executing a logical computation with the scrambling code and each physical address to individually obtain a mapping address; and verifying the number of the faulty memory cells corresponding to the mapping address of the same page is up to a maximum tolerance. - View Dependent Claims (7, 8, 9)
-
Specification