ENTITLEMENT VECTOR FOR MANAGING RESOURCE ALLOCATION

• US 20150020075A1
• Filed: 07/18/2014
• Published: 01/15/2015
• Est. Priority Date: 07/19/2011
• Status: Active Grant

• Current Assignee: RPX Corporation
• Original Assignee: Elwha LLC (Intellectual Ventures LLC)
• Inventors: Glew, Andrew F., Gerrity, Daniel A., Tegreene, Clarence T.
• Granted Patent: US 9,558,034 B2
• Time in Patent Office: Days
• US Class Current: 718/101
• CPC Class Codes: G06F 2209/485 Resource constraint
• CPC Class Codes: G06F 2209/504 Resource capping
• CPC Class Codes: G06F 9/30145 Instruction analysis, e.g. decoding, instruction word fields
• CPC Class Codes: G06F 9/468 Specific access rights for resources, e.g. using capability register
• CPC Class Codes: G06F 9/4881 Scheduling strategies for dispatcher, e.g. round robin, multi-level priority queues
• CPC Class Codes: G06F 9/50 Allocation of resources, e.g. of the central processing unit [CPU]
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

An embodiment or embodiments of an information handling apparatus can use an entitlement vector to simultaneously manage and activate entitlement of objects and processes to various resources independently from one another. An information handling apparatus can comprise an entitlement vector operable to specify resources used by at least one object of a plurality of object. The information handling apparatus can further comprise a scheduler operable to schedule a plurality of threads based at least partly on entitlement as specified by the entitlement vector.

Claims

1-65. -65. (canceled)

66. A computer program product comprising:

one or more non-transitory computer-readable media bearing at least;

one or more program instructions operable to provide an entitlement vector;

one or more program instructions operable to specify, in the entitlement vector, resources used by at least one object of a plurality of objects; and

one or more program instructions operable to schedule a plurality of threads based at least partly on entitlement as specified by the entitlement vector.

67. The computer program product according to claim 66 further comprising:

one or more program instructions operable to provide a plurality of instruction pointers;

one or more program instructions operable to indicate respective ones of the plurality of threads for execution using the plurality of instruction pointers; and

one or more program instructions operable to associate the plurality of instruction pointers and/or threads with ones of a respective plurality of entitlement vectors.

68. The computer program product according to claim 66 further comprising:

one or more program instructions operable to provide a plurality of entitlement vectors;

one or more program instructions operable to specify, in the entitlement vectors, resources used by at least one object of a plurality of objects; and

one or more program instructions operable to schedule a process of a plurality of processes wherein ones of the plurality of entitlement vectors respectively associated with ones of the plurality of processes are arguments of the least one function.

69. The computer program product according to claim 66 further comprising:

one or more program instructions operable to monitor resource usage during execution of a plurality of processes; and

one or more program instructions operable to indicate the resource usage in a usage vector.

70-73. -73. (canceled)

74. A system for handling information comprising:

circuitry for providing an entitlement vector;

circuitry for specifying in the entitlement vector one or more resources used by at least one object of a plurality of objects; and

circuitry for scheduling a plurality of threads based at least partly on entitlement as specified by the entitlement vector.

75. The system according to claim 74, further comprising:

circuitry for providing a plurality of instruction pointers;

circuitry for indicating respective one or more of the plurality of threads for execution using the plurality of instruction pointers; and

circuitry for associating the plurality of instruction pointers and/or threads with one or more of a respective plurality of entitlement vectors.

76. The system according to claim 74, further comprising:

circuitry for respectively associating a plurality of entitlement vectors with a plurality of threads; and

circuitry for scheduling the plurality of threads based at least partly on mutual comparison of the plurality of entitlement vectors.

77. The system according to claim 74, further comprising:

circuitry for assigning priority among the plurality of threads using the entitlement as specified by the entitlement vector.

78. The system according to claim 74, further comprising:

circuitry for inserting random fluctuation into the priority among the plurality of threads.

79. The system according to claim 74, further comprising:

circuitry for inserting random fluctuation into the priority using a randomization algorithm that includes at least one of a Boltzmann search, a simulated annealing, a hop-around, an oscillation for detecting a local maximum, a comparing new to previous optimum, or a lateral computing technique.

80. The system according to claim 74, further comprising:

circuitry for modifying the entitlement vector to at least partially ensure correct context of the entitlement vector during context switching.

81. The system according to claim 74, further comprising:

circuitry for modifying the entitlement vector using an algorithm that includes at least a library call operable to ensure correct context of the entitlement vector during context switching.

82. The system according to claim 74, further comprising:

circuitry for scheduling one or more of the plurality of threads wherein one or more of a plurality of entitlement vectors respectively associated with one or more of the plurality of threads are arguments of at least one function; and

circuitry for executing the at least one function.

83. The system according to claim 74, further comprising:

circuitry for scheduling one or more of the plurality of threads wherein one or more of the plurality of entitlement vectors respectively associated with one or more of the plurality of threads and resource usage level are arguments of at least one function; and

circuitry for executing the at least one function.

84. The system according to claim 74, further comprising:

circuitry for scheduling one or more of the plurality of threads wherein one or more of the plurality of entitlement vectors respectively associated with one or more of the plurality of threads, a weight, or a resource usage level are arguments of at least one function; and

circuitry for executing the at least one function.

85. The system according to claim 74, further comprising:

circuitry for scheduling one or more of the plurality of threads wherein for a thread, priority_i is determined by a comparison of weight times entitlement vector_i to resource usage level_i over a plurality of cycles i; and

circuitry for executing the at least one function.

86. The system according to claim 74, further comprising:

circuitry for scheduling one or more of the plurality of threads wherein for a thread, priority is determined at least partly by a comparison of a sum of weight times entitlement vector_i over a plurality of cycles i to resource usage level; and

circuitry for executing the at least one function.

87. The system according to claim 74, further comprising:

circuitry for monitoring resource usage during execution to at least partially indicate the resource usage in a usage vector.

88. The system according to claim 74, further comprising:

circuitry for monitoring resource usage; and

circuitry for modifying the entitlement vector based on the resource usage.

89. The system according to claim 74, further comprising:

circuitry for monitoring resource usage;

circuitry for modifying the entitlement vector based on the resource usage; and

circuitry for comparing the modified entitlement vector to at least one of a user-set or default initial entitlement vector.

90. The system according to claim 74, further comprising:

circuitry for monitoring resource usage;

circuitry for modifying the entitlement vector based on the resource usage; and

circuitry for storing a history of one or more entitlement vectors in an entitlement vector memory.

91. The system according to claim 74, further comprising:

circuitry for monitoring resource usage;

circuitry for modifying the entitlement vector based on the resource usage; and

circuitry for merging the modified entitlement vector into an evolving entitlement vector.

92. The system according to claim 74, further comprising:

circuitry for indicating, in a priority vector, priority for scheduling a plurality of threads as a function of a combination of entitlement as specified by the entitlement vector and resource usage as specified by a usage vector.

93. The system according to claim 74, wherein:

the resources include at least one of one or more physical/logical resources or one or more operational resources, including at least one of;

one or more physical/logical resources including one or more of a processor, a central processing unit (CPU), a graphics hardware, a network controller, a memory, a memory management, hardware, microarchitecture, a sound card, a video card, a network interface, an instruction set architecture (ISA), a library call, a library function, a software object, a compiler, or an operating system;

or

one or more operational resources including one or more of power, voltage, current, an electron, frequency, an execution cycle, battery consumption, battery life, a constraint, temperature, or a measurable phenomenon.

94. A system for handling information comprising:

circuitry for providing a plurality of entitlement vectors;

circuitry for specifying, in one or more of the plurality of entitlement vectors, one or more resource used by at least one object of a plurality of objects; and

circuitry for scheduling at least one process of a plurality of processes wherein one or more of the plurality of entitlement vectors respectively associated with one or more of the plurality of processes are one or more arguments of the least one function.

95. The system according to claim 94, further comprising:

circuitry for executing the at least one function.

96. The system according to claim 94, further comprising:

scheduling one or more of the plurality of processes wherein one or more of the plurality of entitlement vectors respectively associated with one or more of the plurality of processes and resource usage level are one or more arguments of the at least one function.

97. The system according to claim 94, further comprising:

circuitry for scheduling one or more of the plurality of processes wherein one or more of the plurality of entitlement vectors respectively associated with one or more of the plurality of processes, a weight, or a resource usage level are one or more arguments of the at least one function.

98. The system according to claim 94, further comprising:

circuitry for scheduling one or more of the plurality of processes wherein for at least one process, priority_i is determined by a comparison of weight times entitlement vector_i to resource usage level_i over a plurality of cycles i.

99. The system according to claim 94, further comprising:

circuitry for scheduling one or more of the plurality of processes wherein for at least one process, priority is determined at least partly by a comparison of a sum of weight times entitlement vector_i over a plurality of cycles i to resource usage level.

100. A system for handling information comprising:

circuitry for providing an entitlement vector;

circuitry for specifying, in the entitlement vector, one or more resources used by at least one object of a plurality of objects;

circuitry for monitoring resource usage during execution of a plurality of processes; and

circuitry for indicating the resource usage in a usage vector.

101. The system according to claim 100, further comprising:

circuitry for modifying the entitlement vector based on the resource usage.

102. The system according to claim 100, further comprising:

circuitry for modifying the entitlement vector based on the resource usage; and

circuitry for comparing the modified entitlement vector to a user-set or default initial entitlement vector.

103. The system according to claim 100, further comprising:

circuitry for modifying the entitlement vector based on the resource usage; and

circuitry for storing a history of entitlement vectors in an entitlement vector memory.

104. The system according to claim 100, further comprising:

circuitry for modifying the entitlement vector based on the resource usage; and

circuitry for merging the modified entitlement vector into an evolving entitlement vector.

105. The system according to claim 100, further comprising:

circuitry for indicating, in a priority vector, priority for scheduling a plurality of processes as a function of a combination of entitlement as specified by the entitlement vector and resource usage as specified by a usage vector.