III-V SEMICONDUCTOR DEVICE HAVING SELF-ALIGNED CONTACTS

• US 20150021662A1
• Filed: 07/18/2013
• Published: 01/22/2015
• Est. Priority Date: 07/18/2013
• Status: Active Grant

• Current Assignee: Globalfoundries US Incorporated (GlobalFoundries, Inc.)
• Original Assignee: International Business Machines Corporation
• Inventors: Basu, Anirban, Majumdar, Amlan, Sun, Yanning
• Granted Patent: US 9,666,684 B2
• Time in Patent Office: Days
• US Class Current: 257/192
• CPC Class Codes: H01L 29/205 in different semiconductor regions , e.g. heterojunctions
• CPC Class Codes: H01L 29/41775 characterised by the proximity or the relative position of the source or drain electrode and the gate electrode, e.g. the source or drain electrode separated from the gate electrode by side-walls or spreading around or above the gate electrode
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/66462 with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
• CPC Class Codes: H01L 29/7784 with delta or planar doped donor layer H01L29/7785 takes precedence
• CPC Class Codes: H01L 29/78 with field effect produced by an insulated gate H01L29/7725, H01L29/775, H01L29/778 take precedence

Abstract

A method including forming a III-V compound semiconductor-containing heterostructure, forming a gate dielectric having a dielectric constant greater than 4.0 positioned within a gate trench, the gate trench formed within the III-V compound semiconductor-containing heterostructure, and forming a gate conductor within the gate trench on top of the gate dielectric, the gate conductor extending above the III-V compound semiconductor heterostructure. The method further including forming a pair of sidewall spacers along opposite sides of a portion of the gate conductor extending above the III-V compound semiconductor-containing heterostructure and forming a pair of source-drain contacts self-aligned to the pair of sidewall spacers.

Claims

1. A method comprising:

forming a dielectric layer above a III-V compound semiconductor-containing heterostructure;

forming a gate dielectric having a dielectric constant greater than 4.0 positioned within a gate trench, the gate trench formed within the dielectric layer and the III-V compound semiconductor-containing heterostructure;

forming a gate conductor within the gate trench on top of the gate dielectric, the gate conductor extending above the III-V compound semiconductor heterostructure;

forming a pair of sidewall spacers along opposite sides of a portion of the gate conductor extending above the III-V compound semiconductor-containing heterostructure; and

forming a pair of source-drain contacts self-aligned to the pair of sidewall spacers.

2. The method of claim 1, wherein forming a III-V compound semiconductor-containing heterostructure comprises:

forming a III-V compound semiconductor buffer layer on an upper surface of a substrate;

forming a III-V compound semiconductor channel layer on an upper surface of the III-V compound semiconductor buffer layer;

forming a III-V compound semiconductor barrier layer on an upper surface of the III-V compound semiconductor channel layer; and

forming a III-V compound semiconductor cap layer on an upper surface of the III-V compound semiconductor barrier layer.

3. The method of claim 1, further comprises:

doping a region of the III-V compound semiconductor-containing heterostructure with an element from Group IV, II, or VI of the Periodic Table of Elements.

4. The method of claim 1, further comprising:

forming an inner spacer along a vertical sidewall of the gate trench before forming the gate dielectric.

5. The method of claim 1, wherein the dielectric layer comprises a dielectric material having positive etch selectivity from a dielectric material of the pair of sidewall spacers.

6. The method of claim 1, wherein forming the pair of source-drain contacts self-aligned to the pair of sidewall spacers comprises:

depositing a blanket layer of metal on top of the pair of sidewall spacers and the III-V compound semiconductor-containing heterostructure;

annealing the blanket layer of metal and the III-V compound semiconductor-containing heterostructure causing the blanket layer of metal to react with an upper layer of the III-V compound semiconductor-containing heterostructure, and form the pair of source-drain contacts self-aligned to the pair of sidewall spacers, wherein an edge of each individual source-drain contacts is aligned with an outside edge of each individual sidewall spacer; and

removing an unreacted portion of the blanket layer of metal.

7. The method of claim 1, wherein a portion of the gate conductor above the III-V compound semiconductor heterostructure is wider than a portion of the gate conductor within the III-V compound semiconductor heterostructure.

8. A method comprising:

forming a III-V compound semiconductor-containing heterostructure;

forming a gate trench in a dielectric layer and the III-V compound semiconductor-containing heterostructure, the dielectric layer located above the III-V compound semiconductor-containing heterostructure, and the gate trench extending from a top surface of the dielectric layer down to a channel layer of III-V compound semiconductor-containing heterostructure;

forming a gate dielectric within the gate trench;

forming a gate conductor within the gate trench on top of the gate dielectric, a portion of the gate conductor extending above the III-V compound semiconductor-containing heterostructure being wider than a portion of the gate conductor within the gate trench;

forming a pair of sidewall spacers along opposite sides of a portion of the gate conductor extending above the dielectric layer;

removing a portion of the dielectric layer selective to the III-V compound semiconductor-containing heterostructure and selective to the pair of sidewall spacers, a remaining portion of the dielectric layer remains below each of the sidewall spacers and above the III-V compound heterostructure; and

forming a pair of source-drain contacts within the III-V compound semiconductor-containing heterostructure and self-aligned to the pair of sidewall spacers, wherein an edge of each individual source-drain contact is aligned with an outside edge of each individual sidewall spacer.

9. The method of claim 8, wherein forming a III-V compound semiconductor-containing heterostructure comprises:

forming a III-V compound semiconductor buffer layer on an upper surface of a substrate;

forming a III-V compound semiconductor channel layer on an upper surface of the III-V compound semiconductor buffer layer;

forming a III-V compound semiconductor barrier layer on an upper surface of the III-V compound semiconductor channel layer; and

forming a III-V compound semiconductor cap layer on an upper surface of the III-V compound semiconductor barrier layer.

10. The method of claim 8 further comprises:

doping a region of the III-V compound semiconductor-containing heterostructure with an element from Group IV, II, or VI of the Periodic Table of Elements.

11. The method of claim 8, further comprising:

forming an inner spacer along a vertical sidewall of the gate trench before forming the gate dielectric.

12. The method of claim 8, wherein the dielectric layer comprises a dielectric material having positive etch selectivity from a dielectric material of the pair of sidewall spacers.

13. The method of claim 8, wherein forming the pair of source-drain contacts self-aligned to the pair of sidewall spacers comprises:

depositing a blanket layer of metal on top of the pair of sidewall spacers and the III-V compound semiconductor-containing heterostructure;

annealing the blanket layer of metal and the III-V compound semiconductor-containing heterostructure causing the blanket layer of metal to react with an upper layer of the III-V compound semiconductor-containing heterostructure, and form the pair of source-drain contacts self-aligned to the pair of sidewall spacers; and

removing an unreacted portion of the blanket layer of metal.

14. A structure comprising:

a III-V compound semiconductor-containing heterostructure;

a gate conductor partially embedded in the III-V compound semiconductor-containing heterostructure, the gate conductor extending from above the III-V compound semiconductor-containing heterostructure down into the III-V compound semiconductor-containing heterostructure;

a gate dielectric positioned along a bottom and opposite sides of the gate conductor, the gate dielectric located between the gate conductor and the III-V compound semiconductor-containing heterostructure;

a pair of sidewall spacers positioned on opposite sides of the gate conductor above a dielectric layer, the dielectric layer being above the III-V compound semiconductor-containing heterostructure; and

a pair of source-drain contacts located within the III-V compound semiconductor-containing heterostructure, and self-aligned to the pair of sidewall spacers.

15. The structure of claim 14, wherein the III-V compound semiconductor-containing heterostructure comprises:

a III-V compound semiconductor buffer layer on an upper surface of a substrate;

a III-V compound semiconductor channel layer on an upper surface of the III-V compound semiconductor buffer layer;

a III-V compound semiconductor barrier layer on an upper surface of the III-V compound semiconductor channel layer; and

a III-V compound semiconductor cap layer on an upper surface of the III-V compound semiconductor barrier layer.

16. The structure of claim 14, wherein the pair of source-drain contacts are positioned in a top layer of the III-V compound semiconductor-containing heterostructure.

17. The structure of claim 14, wherein the gate conductor extends from above the III-V compound semiconductor-containing hetero structure down to a channel layer within the III-V compound semiconductor-containing heterostructure.

18. The structure of claim 14, wherein the gate conductor extends from above the III-V compound semiconductor-containing hetero structure down to a barrier layer within the III-V compound semiconductor-containing heterostructure.

19. The structure of claim 14, further comprising:

an inner spacer adjacent to a sidewall of the gate conductor, the inner spacer separating the gate dielectric layer from the III-V compound semiconductor-containing heterostructure.

20. The structure of claim 14, further comprising:

a dielectric layer below each of the sidewall spacers and above the III-V compound semiconductor-containing heterostructure.