METHODS OF FORMING SEMICONDUCTOR DEVICE WITH SELF-ALIGNED CONTACT ELEMENTS AND THE RESULTING DEVICES

• US 20150021683A1
• Filed: 07/22/2013
• Published: 01/22/2015
• Est. Priority Date: 07/22/2013
• Status: Active Grant

• Current Assignee: GlobalFoundries, Inc.
• Original Assignee: GlobalFoundries, Inc.
• Inventors: Xie, Ruilong, Cai, Xiuyu, Cheng, Kangguo, Khakifirooz, Ali
• Granted Patent: US 9,153,498 B2
• Time in Patent Office: Days
• US Class Current: 257/330
• CPC Class Codes: H01L 21/7682 the dielectric comprising air gaps
• CPC Class Codes: H01L 21/76885 By forming conductive members before deposition of protective insulating material, e.g. pillars, studs
• CPC Class Codes: H01L 21/76897 Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step self-aligned silicidation on field effect transistors H01L29/665
• CPC Class Codes: H01L 21/823425 manufacturing common source or drain regions between a plurality of conductor-insulator-semiconductor structures
• CPC Class Codes: H01L 21/823475 interconnection or wiring or contact manufacturing related aspects
• CPC Class Codes: H01L 29/42364 characterised by the insulating layer, e.g. thickness or uniformity H01L29/42324 and H01L29/4234 take precedence
• CPC Class Codes: H01L 29/6653 using the removal of at least part of spacer, e.g. disposable spacer
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/66628 recessing the gate by forming single crystalline semiconductor material at the source or drain location
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Abstract

One method disclosed herein includes forming a sacrificial etch stop material in a recess above a replacement gate structure, with the sacrificial etch stop material in position, forming a self-aligned contact that is conductively coupled to the source/drain region, after forming the self-aligned contact, performing at least one process operation to expose and remove the sacrificial etch stop material in the recess so as to thereby re-expose the recess, and forming a third layer of insulating material in at least the re-exposed recess.

Claims

1. A method of forming a transistor, comprising:

forming a recess above a recessed replacement gate structure that is positioned at least partially within a gate cavity that is laterally defined by sidewall spacers positioned in a first layer of insulating material;

forming a sacrificial etch stop material in said recess;

forming a second layer of insulating material above at least said sacrificial etch stop material and said first layer of insulating material;

with said sacrificial etch stop material in position, performing at least one first etching process to form a self-aligned contact opening that extends through at least said second layer of insulating material and said first layer of insulating material and thereby exposes a source/drain region of said transistor;

with said sacrificial etch stop material in position, forming a self-aligned contact in said self-aligned contact opening that is conductively coupled to said source/drain region;

after forming said self-aligned contact, performing at least one process operation to expose and remove said sacrificial etch stop material in said recess so as to thereby re-expose said recess; and

forming a third layer of insulating material in at least said re-exposed recess.

2. The method of claim 1, wherein said layer of insulating material has an upper surface and wherein said recess has a lower surface that is positioned at a level that is below said upper surface of said layer of insulating material.

3. The method of claim 1, wherein forming said recess comprises:

forming a gate cap layer above said recessed replacement gate structure; and

performing at least one second etching process to remove a portion of said gate cap layer and a portion of said sidewall spacers so as to thereby define said recess.

4. The method of claim 1, wherein forming said recess comprises performing at least one second etching process to remove a portion of at least said sidewall spacers so as to thereby define said recess.

5. The method of claim 1, further comprising forming a V_o conductive contact in said third layer of insulating material, wherein said V_o conductive contact is conductively coupled to said self-aligned contact.

6. The method of claim 1, wherein said sacrificial etch stop material is comprised of a metal, a metal compound, polysilicon or amorphous silicon.

7. The method of claim 1, wherein forming said sacrificial etch stop layer in said gate cap recess comprises:

depositing a layer of etch stop material in said recess; and

performing at least one CMP process to remove portions of said layer of etch stop material positioned outside of said recess.

8. The method of claim 1, wherein performing said at least one process operation to expose said sacrificial etch stop material in said recess comprises performing at least one of a CMP process operation and an etching process operation.

9. The method of claim 1, wherein said recessed replacement gate structure is comprised of a high-k gate insulation layer and at least one layer of metal.

10. A method of forming a transistor, comprising:

forming a gate cap layer above a recessed replacement gate structure that is positioned within a gate cavity that is laterally defined by sidewall spacers;

performing at least one first etching process to remove a portion of said gate cap layer and a portion of said sidewall spacers so as to thereby define a recessed gate cap layer and a gate cap recess formed thereabove;

forming a sacrificial etch stop material in said gate cap recess;

forming a first layer of insulating material above at least said sacrificial etch stop material;

with said sacrificial etch stop material in position, performing at least one second etching process to form a self-aligned contact opening that extends through at least said first layer of insulating material and exposes a source/drain region of said transistor;

forming an initial self-aligned contact in said self-aligned contact opening that is conductively coupled to said source/drain region;

after forming said self-aligned contact, performing at least one process operation to expose said sacrificial etch stop material in said gate cap recess and remove a portion of said initial self-aligned contact so as to thereby define a reduced-height self-aligned contact;

removing said exposed sacrificial etch stop material in said gate cap recess so as to thereby expose said recessed gate cap layer; and

forming a second layer of insulating material above said exposed recessed gate cap layer.

11. The method of claim 10, further comprising forming a V_O conductive contact in said second layer of insulating material, wherein said V_O conductive contact is conductively coupled to said reduced-height self-aligned contact.

12. The method of claim 10, wherein forming said sacrificial etch stop material in said gate cap recess comprises:

depositing a layer of etch stop material in said gate cap recess; and

performing at least one CMP process to remove portions of said layer of etch stop material positioned outside of said gate cap recess.

13. The method of claim 10, wherein performing said at least one process operation to expose said sacrificial etch stop material in said gate cap recess and remove said portion of said initial self-aligned contact comprises performing at least one of a CMP process operation and an etching process operation.

14. A method of forming a transistor, comprising:

forming a sacrificial gate structure above a semiconductor substrate and a first gate cap layer above said sacrificial gate structure;

forming sidewall spacers adjacent said sacrificial gate structure;

forming a first layer of insulating material above said substrate adjacent said sidewall spacers;

performing at least one first etching process to remove said first gate cap layer and said sacrificial gate structure so as to thereby define a gate cavity that is laterally defined by sidewall spacers;

forming a recessed replacement gate structure in said gate cavity;

forming a second gate cap layer above a recessed replacement gate structure;

performing at least one second etching process to remove a portion of said second gate cap layer and a portion of said sidewall spacers so as to thereby define a recessed second gate cap layer and a gate cap recess formed thereabove;

forming a sacrificial etch stop material in said gate cap recess;

forming a second layer of insulating material above at least said sacrificial etch stop material;

with said sacrificial etch stop material in position, performing at least one second etching process to form a self-aligned contact opening that extends through at least said second layer of insulating material and said first layer of insulating material and exposes a source/drain region of said transistor;

forming an initial self-aligned contact in said self-aligned contact opening that is conductively coupled to said source/drain region;

after forming said self-aligned contact, performing at least one process operation to expose said sacrificial etch stop material in said gate cap recess and remove a portion of said initial self-aligned contact so as to thereby define a reduced-height self-aligned contact;

removing said exposed sacrificial etch stop material in said gate cap recess so as to thereby expose said recessed gate cap layer; and

forming a third layer of insulating material above at least said exposed recessed gate cap layer.

15. The method of claim 14, further comprising forming a V_O conductive contact in said third layer of insulating material, wherein said V_O conductive contact is conductively coupled to said reduced-height self-aligned contact.

16. A method of forming a transistor, comprising:

forming a recessed replacement gate structure that is positioned within a gate cavity that is laterally defined by sidewall spacers;

performing at least one first etching process to remove a portion of at least said sidewall spacers so as to thereby define a recessed gate recess within said gate cavity;

forming a sacrificial etch stop material in said recessed gate recess;

forming a first layer of insulating material above at least said sacrificial etch stop material;

with said sacrificial etch stop material in position, performing at least one second etching process to form a self-aligned contact opening that extends through at least said first layer of insulating material and exposes a source/drain region of said transistor;

forming a self-aligned contact in said self-aligned contact opening that is conductively coupled to said source/drain region;

after forming said self-aligned contact, performing at least one process operation to remove said first layer of insulating material, so as to thereby expose said sacrificial etch stop material;

removing said exposed sacrificial etch stop material so as to thereby expose said recessed replacement gate structure; and

forming a second layer of insulating material on and in contact with at least said exposed recessed replacement gate structure.

17. The method of claim 16, wherein said sacrificial etch stop material is comprised of a metal, a metal compound, polysilicon, or amorphous silicon.

18. The method of claim 16, wherein forming said sacrificial etch stop material in said recessed gate recess comprises:

depositing a layer of sacrificial etch stop material in said recessed gate recess; and

performing at least one CMP process to remove portions of said layer of sacrificial etch stop material positioned outside of said recessed gate recess.

19. A method of forming a transistor, comprising:

forming a sacrificial gate structure above a semiconductor substrate and a first gate cap layer above said sacrificial gate structure;

forming sidewall spacers adjacent said sacrificial gate structure;

forming a first layer of insulating material above said substrate adjacent said sidewall spacers;

performing at least one first etching process to remove said first gate cap layer and said sacrificial gate structure so as to thereby define a gate cavity that is laterally defined by said sidewall spacers;

forming a recessed replacement gate structure in said gate cavity;

performing at least one second etching process to remove a portion of at least said sidewall spacers and define a recessed gate recess within said gate cavity;

forming a sacrificial gate cap material in said recessed gate recess;

forming a second layer of insulating material above at least said sacrificial gate cap material and said first layer of insulating material;

with said sacrificial gate cap material in position, performing at least one third etching process to form a self-aligned contact opening that extends through at least said second layer of insulating material and said first layer of insulating material and exposes a source/drain region of said transistor;

forming a self-aligned contact in said self-aligned contact opening that is conductively coupled to said source/drain region;

after forming said self-aligned contact, performing at least one process operation to remove said second layer of insulating material, so as to thereby expose said sacrificial gate cap material;

removing said exposed sacrificial gate cap material so as to thereby expose said recessed replacement gate structure; and

forming a third layer of insulating material above at least said exposed recessed replacement gate structure.

20. The method of claim 19, wherein said sacrificial gate cap material is comprised of a metal, a metal compound, polysilicon, or amorphous silicon.

21. A transistor device, comprising:

a replacement gate structure positioned above a semiconductor substrate;

sidewall spacers positioned adjacent said replacement gate structure;

a gate cap layer positioned above said replacement gate structure, said gate cap layer having an upper surface that is positioned a first distance above a surface of said substrate;

a first layer of insulating material formed above said substrate adjacent said sidewall spacers, said first layer of insulating material having an upper surface that is positioned a second distance above said surface of said substrate; and

a conductive contact positioned in an opening formed in at least said layer of insulating material, said conductive contact being conductively coupled to a source/drain region of said transistor, said conductive contact having an upper surface that is positioned said second distance above said surface of said substrate, wherein said first distance is less than said second distance.

22. The device of claim 21, further comprising an etch stop liner layer positioned between said sidewall spacers and said layer of insulating material.

23. The device of claim 21, further comprising a V_O contact positioned in a second layer of insulating material positioned above said first layer of insulating material and said gate cap layer, wherein said V_O contact is conductively coupled to said conductive contact.

24. A transistor device, comprising:

a replacement gate structure positioned above a semiconductor substrate, said replacement gate structure having an upper surface;

sidewall spacers positioned adjacent said replacement gate structure, each of said sidewall spacers having an upper surface;

a first layer of insulating material formed above said substrate adjacent said sidewall spacers, said first layer of insulating material having an upper surface, wherein, relative to an upper surface of said substrate, said upper surface of said replacement gate structure and said upper surfaces of said sidewall spacers are positioned at a level below said upper surface of said first layer of insulating material, and wherein said first layer of insulating material, said upper surface of said replacement gate structure and said upper surfaces of said sidewall spacers at least partially define a recessed gate cavity;

a conductive contact positioned in an opening formed in at least said first layer of insulating material, said conductive contact being conductively coupled to a source/drain region of said transistor; and

a second layer of insulating material positioned in at least said recessed gate cavity and above said first layer of insulating material.

25. The device of claim 24, further comprising an etch stop liner layer positioned between said sidewall spacers and said first layer of insulating material.

26. The device of claim 24, wherein said conductive contact comprises an over-hang portion that is vertically positioned above at least a portion of said recessed gate cavity.

27. The device of claim 24, wherein said second layer of insulating material is in contact with said upper surface of said replacement gate structure and each of said upper surfaces of said sidewall spacers.