METHODS OF FORMING SEMICONDUCTOR DEVICE WITH SELF-ALIGNED CONTACT ELEMENTS AND THE RESULTING DEVICES
First Claim
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1. A method of forming a transistor, comprising:
- forming a recess above a recessed replacement gate structure that is positioned at least partially within a gate cavity that is laterally defined by sidewall spacers positioned in a first layer of insulating material;
forming a sacrificial etch stop material in said recess;
forming a second layer of insulating material above at least said sacrificial etch stop material and said first layer of insulating material;
with said sacrificial etch stop material in position, performing at least one first etching process to form a self-aligned contact opening that extends through at least said second layer of insulating material and said first layer of insulating material and thereby exposes a source/drain region of said transistor;
with said sacrificial etch stop material in position, forming a self-aligned contact in said self-aligned contact opening that is conductively coupled to said source/drain region;
after forming said self-aligned contact, performing at least one process operation to expose and remove said sacrificial etch stop material in said recess so as to thereby re-expose said recess; and
forming a third layer of insulating material in at least said re-exposed recess.
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Abstract
One method disclosed herein includes forming a sacrificial etch stop material in a recess above a replacement gate structure, with the sacrificial etch stop material in position, forming a self-aligned contact that is conductively coupled to the source/drain region, after forming the self-aligned contact, performing at least one process operation to expose and remove the sacrificial etch stop material in the recess so as to thereby re-expose the recess, and forming a third layer of insulating material in at least the re-exposed recess.
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Citations
27 Claims
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1. A method of forming a transistor, comprising:
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forming a recess above a recessed replacement gate structure that is positioned at least partially within a gate cavity that is laterally defined by sidewall spacers positioned in a first layer of insulating material; forming a sacrificial etch stop material in said recess; forming a second layer of insulating material above at least said sacrificial etch stop material and said first layer of insulating material; with said sacrificial etch stop material in position, performing at least one first etching process to form a self-aligned contact opening that extends through at least said second layer of insulating material and said first layer of insulating material and thereby exposes a source/drain region of said transistor; with said sacrificial etch stop material in position, forming a self-aligned contact in said self-aligned contact opening that is conductively coupled to said source/drain region; after forming said self-aligned contact, performing at least one process operation to expose and remove said sacrificial etch stop material in said recess so as to thereby re-expose said recess; and forming a third layer of insulating material in at least said re-exposed recess. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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10. A method of forming a transistor, comprising:
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forming a gate cap layer above a recessed replacement gate structure that is positioned within a gate cavity that is laterally defined by sidewall spacers; performing at least one first etching process to remove a portion of said gate cap layer and a portion of said sidewall spacers so as to thereby define a recessed gate cap layer and a gate cap recess formed thereabove; forming a sacrificial etch stop material in said gate cap recess; forming a first layer of insulating material above at least said sacrificial etch stop material; with said sacrificial etch stop material in position, performing at least one second etching process to form a self-aligned contact opening that extends through at least said first layer of insulating material and exposes a source/drain region of said transistor; forming an initial self-aligned contact in said self-aligned contact opening that is conductively coupled to said source/drain region; after forming said self-aligned contact, performing at least one process operation to expose said sacrificial etch stop material in said gate cap recess and remove a portion of said initial self-aligned contact so as to thereby define a reduced-height self-aligned contact; removing said exposed sacrificial etch stop material in said gate cap recess so as to thereby expose said recessed gate cap layer; and forming a second layer of insulating material above said exposed recessed gate cap layer. - View Dependent Claims (11, 12, 13)
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14. A method of forming a transistor, comprising:
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forming a sacrificial gate structure above a semiconductor substrate and a first gate cap layer above said sacrificial gate structure; forming sidewall spacers adjacent said sacrificial gate structure; forming a first layer of insulating material above said substrate adjacent said sidewall spacers; performing at least one first etching process to remove said first gate cap layer and said sacrificial gate structure so as to thereby define a gate cavity that is laterally defined by sidewall spacers; forming a recessed replacement gate structure in said gate cavity; forming a second gate cap layer above a recessed replacement gate structure; performing at least one second etching process to remove a portion of said second gate cap layer and a portion of said sidewall spacers so as to thereby define a recessed second gate cap layer and a gate cap recess formed thereabove; forming a sacrificial etch stop material in said gate cap recess; forming a second layer of insulating material above at least said sacrificial etch stop material; with said sacrificial etch stop material in position, performing at least one second etching process to form a self-aligned contact opening that extends through at least said second layer of insulating material and said first layer of insulating material and exposes a source/drain region of said transistor; forming an initial self-aligned contact in said self-aligned contact opening that is conductively coupled to said source/drain region; after forming said self-aligned contact, performing at least one process operation to expose said sacrificial etch stop material in said gate cap recess and remove a portion of said initial self-aligned contact so as to thereby define a reduced-height self-aligned contact; removing said exposed sacrificial etch stop material in said gate cap recess so as to thereby expose said recessed gate cap layer; and forming a third layer of insulating material above at least said exposed recessed gate cap layer. - View Dependent Claims (15)
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16. A method of forming a transistor, comprising:
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forming a recessed replacement gate structure that is positioned within a gate cavity that is laterally defined by sidewall spacers; performing at least one first etching process to remove a portion of at least said sidewall spacers so as to thereby define a recessed gate recess within said gate cavity; forming a sacrificial etch stop material in said recessed gate recess; forming a first layer of insulating material above at least said sacrificial etch stop material; with said sacrificial etch stop material in position, performing at least one second etching process to form a self-aligned contact opening that extends through at least said first layer of insulating material and exposes a source/drain region of said transistor; forming a self-aligned contact in said self-aligned contact opening that is conductively coupled to said source/drain region; after forming said self-aligned contact, performing at least one process operation to remove said first layer of insulating material, so as to thereby expose said sacrificial etch stop material; removing said exposed sacrificial etch stop material so as to thereby expose said recessed replacement gate structure; and forming a second layer of insulating material on and in contact with at least said exposed recessed replacement gate structure. - View Dependent Claims (17, 18)
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19. A method of forming a transistor, comprising:
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forming a sacrificial gate structure above a semiconductor substrate and a first gate cap layer above said sacrificial gate structure; forming sidewall spacers adjacent said sacrificial gate structure; forming a first layer of insulating material above said substrate adjacent said sidewall spacers; performing at least one first etching process to remove said first gate cap layer and said sacrificial gate structure so as to thereby define a gate cavity that is laterally defined by said sidewall spacers; forming a recessed replacement gate structure in said gate cavity; performing at least one second etching process to remove a portion of at least said sidewall spacers and define a recessed gate recess within said gate cavity; forming a sacrificial gate cap material in said recessed gate recess; forming a second layer of insulating material above at least said sacrificial gate cap material and said first layer of insulating material; with said sacrificial gate cap material in position, performing at least one third etching process to form a self-aligned contact opening that extends through at least said second layer of insulating material and said first layer of insulating material and exposes a source/drain region of said transistor; forming a self-aligned contact in said self-aligned contact opening that is conductively coupled to said source/drain region; after forming said self-aligned contact, performing at least one process operation to remove said second layer of insulating material, so as to thereby expose said sacrificial gate cap material; removing said exposed sacrificial gate cap material so as to thereby expose said recessed replacement gate structure; and forming a third layer of insulating material above at least said exposed recessed replacement gate structure. - View Dependent Claims (20)
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21. A transistor device, comprising:
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a replacement gate structure positioned above a semiconductor substrate; sidewall spacers positioned adjacent said replacement gate structure; a gate cap layer positioned above said replacement gate structure, said gate cap layer having an upper surface that is positioned a first distance above a surface of said substrate; a first layer of insulating material formed above said substrate adjacent said sidewall spacers, said first layer of insulating material having an upper surface that is positioned a second distance above said surface of said substrate; and a conductive contact positioned in an opening formed in at least said layer of insulating material, said conductive contact being conductively coupled to a source/drain region of said transistor, said conductive contact having an upper surface that is positioned said second distance above said surface of said substrate, wherein said first distance is less than said second distance. - View Dependent Claims (22, 23)
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24. A transistor device, comprising:
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a replacement gate structure positioned above a semiconductor substrate, said replacement gate structure having an upper surface; sidewall spacers positioned adjacent said replacement gate structure, each of said sidewall spacers having an upper surface; a first layer of insulating material formed above said substrate adjacent said sidewall spacers, said first layer of insulating material having an upper surface, wherein, relative to an upper surface of said substrate, said upper surface of said replacement gate structure and said upper surfaces of said sidewall spacers are positioned at a level below said upper surface of said first layer of insulating material, and wherein said first layer of insulating material, said upper surface of said replacement gate structure and said upper surfaces of said sidewall spacers at least partially define a recessed gate cavity; a conductive contact positioned in an opening formed in at least said first layer of insulating material, said conductive contact being conductively coupled to a source/drain region of said transistor; and a second layer of insulating material positioned in at least said recessed gate cavity and above said first layer of insulating material. - View Dependent Claims (25, 26, 27)
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Specification