FINFET WITH ELECTRICALLY ISOLATED ACTIVE REGION ON BULK SEMICONDUCTOR SUBSTRATE AND METHOD OF FABRICATING SAME

• US 20150021691A1
• Filed: 07/18/2013
• Published: 01/22/2015
• Est. Priority Date: 07/18/2013
• Status: Active Grant

• Current Assignee: Globalfoundries US Incorporated (GlobalFoundries, Inc.)
• Original Assignee: GlobalFoundries, Inc.
• Inventors: AKARVARDAR, Murat Kerem, JACOB, Ajey Poovannummoottil, FRONHEISER, Jody A.
• Granted Patent: US 9,716,174 B2
• Time in Patent Office: Days
• US Class Current: 257/349
• CPC Class Codes: H01L 21/76224 using trench refilling with dielectric materials trench filling with polycristalline silicon H01L21/763; together with vertical isolation, e.g. trench refilling in a SOI substrate H01L21/76264
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Abstract

A semiconductor stack of a FinFET in fabrication includes a bulk silicon substrate, a selectively oxidizable sacrificial layer over the bulk substrate and an active silicon layer over the sacrificial layer. Fins are etched out of the stack of active layer, sacrificial layer and bulk silicon. A conformal oxide deposition is made to encapsulate the fins, for example, using a HARP deposition. Relying on the sacrificial layer having a comparatively much higher oxidation rate than the active layer or substrate, selective oxidization of the sacrificial layer is performed, for example, by annealing. The presence of the conformal oxide provides structural stability to the fins, and prevents fin tilting, during oxidation. Selective oxidation of the sacrificial layer provides electrical isolation of the top active silicon layer from the bulk silicon portion of the fin, resulting in an SOI-like structure. Further fabrication may then proceed to convert the active layer to the source, drain and channel of the FinFET. The oxidized sacrificial layer under the active channel prevents punch-through leakage in the final FinFET structure.

Claims

1. A method, comprising:

providing a semiconductor stack, comprising;

a semiconductor substrate, comprising a bulk semiconductor material;

a sacrificial layer over the substrate, the sacrificial layer comprising an oxidizable material; and

an active semiconductor layer over the sacrificial layer, wherein the sacrificial layer is substantially more susceptible to oxidation than the active layer and the semiconductor substrate;

etching the semiconductor stack to create at least one fin, each fin comprising a portion of the active layer, a portion of the sacrificial layer and a portion of the substrate; and

electrically isolating the active layer of the at least one fin by converting the sacrificial layer to a dielectric layer, wherein the converting comprises selectively oxidizing the sacrificial layer of the at least one fin while providing physical support therefor.

2. The method of claim 1, wherein the providing comprises epitaxially growing the sacrificial layer.

3. The method of claim 2, wherein the epitaxially growing comprises using a chemical vapor deposition (CVD) based process, and wherein the annealing comprises annealing at a temperature of about 400°

C. to about 1100°

C.

4. The method of claim 1, wherein the selectively oxidizing comprises:

conformally depositing an oxide so as to encapsulate the at least one fin;

and annealing the at least one fin and conformal oxide to locally oxidize the sacrificial layer therein, wherein the conformal oxide provides structural stability for and prevents tilting of the at least one fin during the local oxidation.

5. The method of claim 4, wherein the oxidizable material of the sacrificial layer comprises silicon germanium Si_(1-x)Ge_x, wherein 0<

x<

1, and wherein the dielectric comprises an oxide.

6. The method of claim 5, wherein the semiconductor substrate and the active layer comprise silicon.

7. The method of claim 5, wherein 0.3<

x<

0.7.

8. The method of claim 7, wherein x is about 0.5.

9. The method of claim 1, comprising further processing the semiconductor structure into a FinFET after the selective oxidation, wherein the active layer comprises a source, a drain and a channel between the source and the drain.

10. A semiconductor stack, comprising:

a semiconductor substrate, comprising a bulk semiconductor material; and

at least one fin coupled to the semiconductor substrate and comprising an active region, an inactive region, and a fin separation region directly below the active region and above the inactive region;

wherein each separation region comprises at least one dielectric material.

11. The semiconductor structure of claim 10, wherein the at least one fin comprises the bulk semiconductor material.

12. The semiconductor structure of claim 11, wherein the bulk semiconductor material comprises silicon, and wherein the at least one dielectric material comprises at least one of silicon dioxide, germanium, germanium oxide, germanium crystals, and germanium crystals uniformly dispersed within silicon dioxide.

13. The semiconductor structure of claim 10, wherein the active region of the at least one fin above the separation region comprises a source, a drain and a channel between the source and the drain.

14. A transistor, comprising:

a bulk semiconductor substrate; and

at least one fin, comprising;

a first region, comprising a source, a drain, and a channel between the source and the drain;

a second region, comprising at least one dielectric material directly below the first region; and

a third region below the second region and coupled to the substrate.

15. The transistor of claim 14, wherein the channel is undoped.

16. The transistor of claim 14, wherein the channel comprises one or more impurities.

17. The transistor of claim 16, wherein the channel comprises silicon germanium.

18. The transistor of claim 14, wherein the bulk semiconductor substrate, the first region and the third region comprise silicon, and wherein the at least one dielectric material comprises at least one of silicon dioxide, germanium, germanium oxide, germanium crystals, and germanium crystals uniformly dispersed within silicon dioxide.