Controlled Ion Implantation Into Silicon Carbide Using Channeling And Devices Fabricated Using Controlled Ion Implantation Into Silicon Carbide Using Channeling

• US 20150028350A1
• Filed: 05/19/2014
• Published: 01/29/2015
• Est. Priority Date: 07/26/2013
• Status: Active Grant

• Current Assignee: CREE Incorporated (Wolfspeed, Inc.)
• Original Assignee: CREE Incorporated (Wolfspeed, Inc.)
• Inventors: Suvorov, Alexander V., Pala, Vipindas
• Granted Patent: US 9,768,259 B2
• Time in Patent Office: Days
• US Class Current: 257/77
• CPC Class Codes: H01L 21/046 using ion implantation
• CPC Class Codes: H01L 21/047 characterised by the angle between the ion beam and the crystal planes or the main crystal surface
• CPC Class Codes: H01L 21/26506 in group IV semiconductors
• CPC Class Codes: H01L 21/26586 characterised by the angle between the ion beam and the crystal planes or the main crystal surface
• CPC Class Codes: H01L 21/324 Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering H01L21/20 - H01L21/288 and H01L21/302 - H01L21/322 take precedence
• CPC Class Codes: H01L 29/0619 with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
• CPC Class Codes: H01L 29/0688 characterised by the particular shape of a junction between semiconductor regions
• CPC Class Codes: H01L 29/0878 Impurity concentration or distribution
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/1608 Silicon carbide
• CPC Class Codes: H01L 29/6606 the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
• CPC Class Codes: H01L 29/66068 the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
• CPC Class Codes: H01L 29/665 using self aligned silicidation, i.e. salicide formation of conductive layers comprising silicides H01L21/28518
• CPC Class Codes: H01L 29/66712 Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/7802 Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/7828 without inversion channel, e.g. vertical ACCUFETs, normally-on vertical MISFETs
• CPC Class Codes: H01L 29/861 Diodes
• CPC Class Codes: H01L 29/872 Schottky diodes

Abstract

Methods of forming a semiconductor structure include the use of channeled implants into silicon carbide crystals. Some methods include providing a silicon carbide layer having a crystallographic axis, heating the silicon carbide layer to a temperature of about 300° C. or more, implanting dopant ions into the heated silicon carbide layer at an implant angle between a direction of implantation and the crystallographic axis of less than about 2°, and annealing the silicon carbide layer at a time-temperature product of less than about 30,000° C.-hours to activate the implanted ions.

Claims

1. A method of forming a semiconductor structure, comprising:

providing a silicon carbide layer having a crystallographic axis;

heating the silicon carbide layer to a temperature of about 300°

C. or more;

implanting dopant ions into the heated silicon carbide layer at an implant angle between a direction of implantation and the crystallographic axis of less than about 2°

; and

annealing the silicon carbide layer at a time-temperature product of less than about 30,000°

C.-hours to activate the implanted ions.

2. The method of claim 1, wherein the implant angle is greater than 0.1°

.

3. The method of claim 1, wherein the implant angle is between 0.1°

and 1°

.

4. The method of claim 1, wherein the implant angle is between 0.1°

and 5°

.

5. The method of claim 1, wherein the silicon carbide layer comprises an off-axis silicon carbide layer having an off axis angle between about 2°

and 10°

.

6. The method of claim 1, further comprising controlling the implant angle to reduce a depth of the implanted ions in the silicon carbide layer compared to a depth the implanted ions would have if implanted at an implant angle of 0°

.

7. The method of claim 1, further comprising maintaining the silicon carbide layer at a temperature of about 500°

C. or more during the implantation.

8. The method of claim 1, further comprising maintaining the silicon carbide layer at a temperature of about 1000°

C. or more during the implantation.

9. The method of claim 1, wherein implanting the dopant ions comprises implanting the dopant ions at an implant energy of about 100 keV or less, while controlling the implanted ions to have a depth of greater than 0.1 microns and less than 1.0 microns.

10. The method of claim 9, wherein implanting the dopant ions comprises implanting the dopant ions at an implant energy of about 100 keV or less, while controlling the implanted ions to have a depth of greater than 0.2 microns and less than 0.5 microns.

11. The method of claim 1, wherein implanting the dopant ions comprises implanting the dopant ions at an implant energy of about 50 key or less, while controlling the implanted ions to have a depth of greater than 0.1 microns and less than 1.0 microns.

12. The method of claim 11, wherein implanting the dopant ions comprises implanting the dopant ions at an implant energy of about 50 keV or less, while controlling the implanted ions to have a depth of greater than 0.2 microns and less than 0.5 microns.

13. The method of claim 1, wherein implanting the dopant ions comprises implanting the dopant ions at an implant energy of about 30 keV or less, while controlling the implanted ions to have a depth of greater than 0.1 microns and less than 1.0 microns.

14. The method of claim 13, wherein implanting the dopant ions comprises implanting the dopant ions at an implant energy of about 30 keV or less, while controlling the implanted ions to have a depth of greater than 0.2 microns and less than 0.3 microns.

15. The method of claim 1, wherein implanting the dopant ions comprises implanting the dopant ions at an implant energy of about 10 keV or less, while controlling the implanted ions to have a depth of greater than 0.1 microns and less than 0.5 microns.

16. The method of claim 1, wherein the implanted ions have a depth in the silicon carbide layer that is less than a depth the implanted ions would have if implanted at room temperature.

17. The method of claim 1, wherein the silicon carbide layer is free of a screening layer when the dopant ions are implanted therein.

18. The method of claim 1, further comprising:

providing a mask on the silicon carbide layer, the mask exposing portions of the silicon carbide layer, wherein the mask has a thickness less than 60% of a thickness that would otherwise be required for implants performed at an energy level needed to obtain the same implant depth without channeling, and wherein implanting the dopant ions comprises implanting the dopant ions through the mask.

19-54. -54. (canceled)

55. An article of manufacture, comprising:

a silicon carbide layer;

an implanted region in the silicon carbide layer containing implanted dopant atoms, wherein the implanted region extends to a depth of from about 2.5 microns to about 4.5 microns into silicon carbide layer and has a doping concentration that varies by less than about 25% from a peak concentration over a depth of at least about 1 micron.

56. The article of claim 55, wherein the implanted region has a doping concentration that varies by less than about 25% from a peak concentration over a depth of at least about 1.5 microns.

57. The article of claim 56, wherein the implanted region has a doping concentration that varies by less than about 25% from a peak concentration over a depth of at least about 1.75 microns.