ADHESIVE WAFER BONDING WITH CONTROLLED THICKNESS VARIATION

• US 20150028362A1
• Filed: 07/26/2013
• Published: 01/29/2015
• Est. Priority Date: 07/26/2013
• Status: Active Grant

• Current Assignee: Apple Inc.
• Original Assignee: LuxVue Techonology Corporation (Apple Inc.)
• Inventors: Chan, Clayton Ka Tsun, Bibl, Andreas
• Granted Patent: US 9,087,764 B2
• Time in Patent Office: Days
• US Class Current: 257/88
• CPC Class Codes: H01L 2224/05139 Silver [Ag] as principal constituent
• CPC Class Codes: H01L 2224/05155 Nickel [Ni] as principal constituent
• CPC Class Codes: H01L 2224/05166 Titanium [Ti] as principal constituent
• CPC Class Codes: H01L 2224/05169 Platinum [Pt] as principal constituent
• CPC Class Codes: H01L 2224/05609 Indium [In] as principal constituent
• CPC Class Codes: H01L 2224/05611 Tin [Sn] as principal constituent
• CPC Class Codes: H01L 2224/05613 Bismuth [Bi] as principal constituent
• CPC Class Codes: H01L 2224/05639 Silver [Ag] as principal constituent
• CPC Class Codes: H01L 2224/05644 Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/29117 the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
• CPC Class Codes: H01L 2224/29138 the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
• CPC Class Codes: H01L 2224/29144 Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/29155 Nickel [Ni] as principal constituent
• CPC Class Codes: H01L 2224/29186 with a principal constituent of the material being a non metallic, non metalloid inorganic material
• CPC Class Codes: H01L 2224/2919 with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
• CPC Class Codes: H01L 2224/75252 in the upper part of the bonding apparatus, e.g. in the bonding head
• CPC Class Codes: H01L 2224/7598 specially adapted for batch processes
• CPC Class Codes: H01L 2224/83192 wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/83409 Indium [In] as principal constituent
• CPC Class Codes: H01L 2224/83411 Tin [Sn] as principal constituent
• CPC Class Codes: H01L 2224/83444 : Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/8349 : with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
• CPC Class Codes: H01L 2224/83815 : Reflow soldering
• CPC Class Codes: H01L 2224/8382 : Diffusion bonding
• CPC Class Codes: H01L 2224/83895 : between electrically conductive surfaces, e.g. copper-copper direct bonding, surface activated bonding
• CPC Class Codes: H01L 24/00 : Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
• CPC Class Codes: H01L 24/05 : of an individual bonding area
• CPC Class Codes: H01L 24/29 : of an individual layer connector
• CPC Class Codes: H01L 24/75 : Apparatus for connecting with bump connectors or layer connectors
• CPC Class Codes: H01L 24/83 : using a layer connector
• CPC Class Codes: H01L 24/95 : at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
• CPC Class Codes: H01L 27/156 : two-dimensional arrays
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01004 : Beryllium [Be]
• CPC Class Codes: H01L 2924/01028 : Nickel [Ni]
• CPC Class Codes: H01L 2924/01032 : Germanium [Ge]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/013 : Alloys
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/053 : Oxides composed of metals from groups of the periodic table
• CPC Class Codes: H01L 2924/0665 : Epoxy resin
• CPC Class Codes: H01L 2924/10155 : being other than a cuboid
• CPC Class Codes: H01L 2924/12041 : LED
• CPC Class Codes: H01L 2924/12042 : LASER
• CPC Class Codes: H01L 2924/1461 : MEMS
• CPC Class Codes: H01L 33/005 : Processes
• CPC Class Codes: H01L 33/0093 : Wafer bonding; Removal of the growth substrate
• CPC Class Codes: H01L 33/06 : within the light emitting region, e.g. quantum confinement structure or tunnel barrier

Abstract

A method and structure for forming an array of micro devices is disclosed. An array of micro devices is formed over an array of stabilization posts included in a stabilization layer. The stabilization layer is bonded to a spacer side of a carrier substrate. The spacer side of the carrier substrate includes raised spacers extending from a spacer-side surface of the carrier substrate.

Claims

1. A method of forming an array of micro devices comprising:

patterning a device layer to form an array of micro device mesa structures over a handle substrate;

forming a patterned sacrificial layer including an array of openings over the corresponding array of micro device mesa structures;

forming a stabilization layer over the patterned sacrificial layer and within the array of openings; and

bonding the stabilization layer to a spacer side of a carrier substrate, wherein the spacer side of the carrier substrate includes raised spacers extending from a spacer-side surface.

2. The method of claim 1, wherein each micro device mesa structure includes a p-doped layer, an n-doped layer, and a quantum well layer between the p-doped layer and the n-doped layer.

3. The method of claim 1, wherein bonding the stabilization layer to the spacer side includes positioning the raised spacers upon at least a portion of the patterned sacrificial layer.

4. The method of claim 1, further comprising:

forming the array of openings in the patterned sacrificial layer directly over an array of conductive contacts of the corresponding array of micro device mesa structures.

5. The method of claim 1, wherein bonding the stabilization layer to the spacer side of the carrier substrate comprises curing the stabilization layer.

6. The method of claim 5, wherein the stabilization layer is formed of a thermoset material.

7. The method of claim 1, further comprising removing the handle substrate after bonding the stabilization layer to the spacer side of the carrier substrate.

8. The method of claim 1, wherein the raised spacers are of a same material as the carrier substrate.

9. The method of claim 1, wherein the raised spacers are formed from the carrier substrate using a subtractive process.

10. The method of claim 1, further comprising:

removing the handle substrate; and

removing the patterned sacrificial layer after removing the handle substrate.

11. The method of claim 1, wherein the array of openings are separated by a pitch of 1 μ

m to 10 μ

m.

12. The method of claim 1, wherein the raised spacers on the carrier substrate outnumber the micro device mesa structures.

13. The method of claim 1, wherein the patterning the device layer to form the array of micro device mesa structures leaves unremoved portions of the device layer between the array of micro device mesa structures, and further comprising removing the unremoved portions of the device layer to form an array of laterally separate micro LED devices after removing the handle substrate.

14. A method of forming an array of micro devices comprising:

forming a patterned sacrificial layer including an array of openings over a device layer;

forming a stabilization layer over the patterned sacrificial layer and within the array of openings;

bonding the stabilization layer to a spacer side of a carrier substrate, wherein the spacer side of the carrier substrate includes raised spacers extending from a spacer-side surface; and

patterning the device layer to form the array of micro devices subsequent to bonding the stabilization layer to the spacer side of the carrier substrate.

15. The method of claim 14, wherein each micro device includes a p-doped layer, an n-doped layer, and a quantum well layer between the p-doped layer and the n-doped layer.

16. The method of claim 14, wherein bonding the stabilization layer to the spacer side includes positioning the raised spacers to rest upon at least a portion of the patterned sacrificial layer.

17. The method of claim 14, further comprising removing a handle substrate prior to patterning the device layer, wherein the handle substrate supports the device layer while the patterned sacrificial layer is formed.

18. The method of claim 14, further comprising:

forming the array of openings in the patterned sacrificial layer directly over an array of conductive contacts formed over the device layer.

19. The method of claim 14, wherein bonding the stabilization layer to the spacer side of the carrier substrate comprises curing the stabilization layer.

20. The method of claim 19, wherein the stabilization layer is formed of a thermoset material.

21. The method of claim 14, further comprising removing the patterned sacrificial layer after patterning the device layer.

22. The method of claim 14, wherein the raised spacers are of a same material as the carrier substrate.

23. The method of claim 14, wherein the array of openings are separated by a pitch of 1 μ

m to 10 μ

m.

24. A structure comprising:

a stabilization layer including an array of stabilization posts;

an array of micro devices formed over the array of stabilization posts; and

a carrier substrate including raised spacers extending from a spacer-side surface of the carrier substrate, wherein the raised spacers extend into the stabilization layer to meet a subset of the stabilization posts in the array of stabilization posts.

25. The structure of claim 24, wherein the micro devices are micro LED devices.

26. The structure of claim 24, wherein each micro device in the array of micro devices includes a bottom surface that is wider than a corresponding stabilization post directly underneath the bottom surface.

27. The structure of claim 24, further comprising a sacrificial layer between the stabilization layer and the array of micro devices, wherein the array of stabilization posts extend into a thickness of the sacrificial layer.

28. The structure of claim 27, wherein the sacrificial layer spans along a side surface of each of the micro devices in the array of micro devices, the side surface running between a top surface and a bottom surface of each micro device in the array.

29. The structure of claim 24, wherein the stabilization layer includes an array of stabilization cavities that include sidewalls surrounding the stabilization posts.

30. The structure of claim 24, further comprising an array of bottom conductive contacts on bottom surfaces of the array of micro devices.

31. The structure of claim 24, wherein the stabilization layer is formed of a thermoset material.

32. The structure of claim 24, wherein a number of the raised spacers extending from the carrier substrate is less than a number of the micro devices formed over the array of stabilization posts.

33. The structure of claim 24, wherein the array of stabilization posts are separated by a pitch of 1 μ

m to 10 μ

m.