SEMICONDUCTOR DEVICE

• US 20150028412A1
• Filed: 09/10/2014
• Published: 01/29/2015
• Est. Priority Date: 03/12/2008
• Status: Active Grant

• Current Assignee: Infineon Technologies Austria Ag (Infineon Technologies AG)
• Original Assignee: Infineon Technologies Austria Ag (Infineon Technologies AG)
• Inventors: Schulze, Hans-Joachim, Voss, Stephan, Zundel, Markus
• Granted Patent: US 9,508,812 B2
• Time in Patent Office: Days
• US Class Current: 257/330
• CPC Class Codes: H01L 27/0207 Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
• CPC Class Codes: H01L 29/0649 Dielectric regions, e.g. SiO2 regions, air gaps
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/402 Field plates
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/41741 for vertical or pseudo-vertical devices
• CPC Class Codes: H01L 29/41775 characterised by the proximity or the relative position of the source or drain electrode and the gate electrode, e.g. the source or drain electrode separated from the gate electrode by side-walls or spreading around or above the gate electrode
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/42372 characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out H01L29/42324 takes precedence
• CPC Class Codes: H01L 29/4238 characterised by the surface lay-out
• CPC Class Codes: H01L 29/51 Insulating materials associated therewith for MIS structures on thin film semiconductor H01L29/4908
• CPC Class Codes: H01L 29/78 with field effect produced by an insulated gate H01L29/7725, H01L29/775, H01L29/778 take precedence
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A semiconductor device is provided that comprises a semiconductor substrate comprising an active area and a peripheral region adjacent the active area and structure positioned in the peripheral region for hindering the diffusion of mobile ions from the peripheral region into the active area.

Claims

1. A semiconductor device comprising:

a semiconductor substrate having a first major surface, an active area and a peripheral region positioned adjacent the active area, the active area comprising a plurality of first trenches and an electrode positioned in the first trenches;

at least one dielectric layer positioned on the first major surface;

a plurality of electrically conductive members positioned in the peripheral region, spatially isolated from one another and extending through the dielectric layer; and

a source metal contact deposited above and forming an electrical contact with the plurality of electrically conductive members.

2. The semiconductor device of claim 1, wherein

the electrically conductive members are arranged in two or more rows.

3. The semiconductor device of claim 2, wherein

the electrically conductive members of adjacent rows are offset with respect to one another.

4. The semiconductor device of claim 1, wherein

in plan view, the electrically conductive members are generally V-shaped.

5. The semiconductor device of claim 1, wherein

the electrically conductive members are positioned adjacent two opposing sides of the active area.

6. The semiconductor device of claim 1, wherein

the electrically conductive members further comprise a plurality of second trenches filled with electrically conductive material, the second trenches extending from the first major surface into the semiconductor substrate.

7. The semiconductor device of claim 6, wherein

the second trenches in plan view have a shape corresponding to the shape of the electrically conductive members in plan view.

8. The semiconductor device of claim 6, wherein

the electrically conductive material protrudes above the first major surface.

9. The semiconductor device of claim 1, wherein

the electrode positioned in the first trenches is electrically isolated from the electrically conductive members.

10. The semiconductor device of claim 1, wherein

the electrode positioned in the first trenches is a gate electrode.

11. The semiconductor device of claim 1, wherein

the peripheral region further comprises a plurality of third trenches electrically connected to the first trenches.

12. The semiconductor device of claim 11, wherein

the first trenches are connected to the third trenches by a fourth trench extending generally perpendicularly to the direction of the first trenches and the third trenches.

13. The semiconductor device of claim 11, wherein

the electrically conductive members further comprise a plurality of second trenches filled with electrically conductive material, the second trenches extending from the first major surface into the semiconductor substrate, wherein at least one second trench is arranged between adjacent pairs or groups of third trenches.

14. The semiconductor device of claim 11, wherein,

in plan view, the plurality of third trenches are laterally offset with respect to the plurality of first trenches.

15. The semiconductor device of claim 11, wherein,

in plan view, at least one third trench meanders between adjacent electrically conductive members.