FINFET STRUCTURES HAVING SILICON GERMANIUM AND SILICON CHANNELS

• US 20150028454A1
• Filed: 07/24/2013
• Published: 01/29/2015
• Est. Priority Date: 07/24/2013
• Status: Active Grant

• Current Assignee: Alsephina Innovations Inc. (Quarterhill Inc. (f/k/a Wi-LAN Inc.))
• Original Assignee: International Business Machines Corporation
• Inventors: CHENG, KANGGUO, KHAKIFIROOZ, ALI, REZNICEK, ALEXANDER, SHAHIDI, GHAVAM G.
• Granted Patent: US 9,093,533 B2
• Time in Patent Office: Days
• US Class Current: 257/616
• CPC Class Codes: H01L 21/02381 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/02532 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/033 comprising inorganic layers
• CPC Class Codes: H01L 21/3065 Plasma etching; Reactive-ion etching
• CPC Class Codes: H01L 21/308 using masks H01L21/3063, H01L21/3065 take precedence
• CPC Class Codes: H01L 21/823431 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 21/823807 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823821 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 21/845 including field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 27/0924 including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 27/1211 combined with field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/16 including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/7855 with at least two independent gates

Abstract

Silicon and silicon germanium fins are formed on a semiconductor wafer or other substrate in a manner that facilitates production of closely spaced nFET and pFET devices. A patterned mandrel layer is employed for forming one or more recesses in the wafer prior to the epitaxial growth of a silicon germanium layer that fills the recess. Spacers are formed on the side walls of the patterned mandrel layer followed by removal of the mandrel layer. The exposed areas of the wafer and silicon germanium layer between the spacers are etched to form fins usable for nFET devices from the wafer and fins usable for pFET devices from the silicon germanium layer.

Claims

1. A method comprising:

forming a patterned mandrel layer on a semiconductor substrate, the patterned mandrel layer including mandrel portions having side walls;

recessing one or more portions of the semiconductor substrate to form one or more trenches within the semiconductor substrate;

epitaxially growing a silicon germanium layer within the one or more trenches;

forming spacers on the side walls of the mandrel portions;

removing the mandrel portions from the semiconductor substrate, and

removing portions of the semiconductor substrate and the silicon germanium layer between the spacers, thereby forming a first plurality of parallel fins from the semiconductor substrate and a second plurality of parallel fins from the silicon germanium layer.

2. The method of claim 1, wherein the semiconductor substrate comprises a bulk silicon substrate.

3. The method of claim 2, further including the step of forming n-type FinFET devices using the first plurality of fins and p-type FinFET devices using the fins formed from the silicon germanium layer.

4. The method of claim 3, wherein the step of forming the patterned mandrel layer further includes forming equally spaced mandrel portions of equal width.

5. The method of claim 2, further including the steps of:

forming a mask over a selected region of the semiconductor substrate and selected mandrel portions in the selected region of the semiconductor substrate prior to recessing the one or more portions of the semiconductor substrate, and

removing the mask following the step of epitaxially growing the silicon germanium layer.

6. The method of claim 2, wherein the fins have heights of less than fifty nanometers.

7. The method of claim 2, wherein the step of removing portions of the semiconductor substrate and the silicon germanium layer between the spacers includes performing a reactive ion etch.

8. The method of claim 2, further including the step of forming a mask on a portion of the semiconductor substrate, a portion of the silicon germanium layer adjoining the semiconductor substrate, and a plurality of the spacers prior to forming the plurality of fins.

9. The method of claim 8, further including the step of forming n-type FinFET devices using the first plurality of fins and p-type FinFET devices using the fins formed from the silicon germanium layer.

10. The method of claim 1, wherein the step of forming the first plurality of fins from the semiconductor substrate and the second plurality of fins from the silicon germanium layer further includes forming at least one fin comprising silicon germanium parallel to and within less than 30 nm of one of the fins formed from the semiconductor substrate.

11. The method of claim 10, wherein the silicon germanium layer has a germanium atomic concentration of ten to sixty percent.

12. A method comprising:

obtaining a structure comprising a semiconductor substrate having a top surface, one or more trenches within the semiconductor substrate, one or more silicon germanium regions within the one or more trenches, each of the one or more silicon germanium regions including a top surface coplanar with the top surface of the semiconductor substrate, a plurality of mandrel portions on the top surface of the substrate, the mandrel portions having sidewalls, and a plurality of spacers on the sidewalls of the mandrel portions, and

forming one or more semiconductor fins from the semiconductor substrate and one or more silicon germanium fins parallel to the one or more semiconductor fins from the one or more silicon germanium regions using sidewall image transfer.

13. The method of claim 12, wherein semiconductor substrate comprises a bulk silicon substrate.

14. The method of claim 13, further including forming at least one n-type FinFET device using the one or more semiconductor fins and at least one p-type FinFET device using the one or more silicon germanium fins.

15. The method of claim 12, wherein the step of forming one or more semiconductor fins from the semiconductor substrate and one or more silicon germanium fins parallel to the one or more semiconductor fins from the one or more silicon germanium regions further includes forming at least one fin comprising silicon germanium within less than 30 nm of one of the fins formed from the semiconductor substrate.

16. The method of claim 12, further including the steps of forming a mask over the top surface of the semiconductor substrate and the top surface of one of the one or more silicon germanium regions, and forming an intermediate region beneath the mask including a silicon portion and a silicon germanium portion adjoining the silicon portion.

17. A structure comprising:

a substrate comprised of crystalline silicon, the substrate including a body portion and one or more first fins comprised of crystalline silicon extending from and integral with the body portion, and

one or more second fins comprising silicon germanium and integral with the body portion of the substrate, the one or more second fins being parallel to the one or more first fins, at least one of the one or more second fins being within less than 30 nm of at least one of the one or more first fins.

18. The structure of claim 17, wherein the one or more second fins include a silicon base integral with the body portion of the substrate and a silicon germanium portion integral with the silicon base.

19. The structure of claim 17, further including a plurality of first and second fins, said first and second fins being equally spaced from each other.

20. The structure of claim 17, wherein the one or more second fins have a germanium atomic concentration of ten to sixty percent.