RECTIFIER CIRCUIT WITH CURRENT INJECTION

• US 20150029771A1
• Filed: 02/22/2013
• Published: 01/29/2015
• Est. Priority Date: 03/30/2012
• Status: Active Grant

• Current Assignee: Schneider Electric Power Drives Gmbh (Schneider Electric SE)
• Original Assignee: Schneider Electric Power Drives Gmbh (Schneider Electric SE)
• Inventors: Hartmann, Michael, Fehringer, Rudolf
• Granted Patent: US 9,444,362 B2
• Time in Patent Office: Days
• US Class Current: 363/126
• CPC Class Codes: H02M 1/0095 Hybrid converter topologies, e.g. NPC mixed with flying capacitor, thyristor converter mixed with MMC or charge pump mixed with buck
• CPC Class Codes: H02M 1/4216 operating from a three-phase input voltage H02M1/4233 takes precedence
• CPC Class Codes: H02M 7/06 using discharge tubes without control electrode or semiconductor devices without control electrode
• CPC Class Codes: H02M 7/2176 comprising a passive stage to generate a rectified sinusoidal voltage and a controlled switching element in series between such stage and the output
• CPC Class Codes: H02M 7/219 in a bridge configuration
• CPC Class Codes: H02M 7/487 Neutral point clamped inverters
• CPC Class Codes: Y02B 70/10 Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

Abstract

The present invention relates to a rectifier circuit with a three-phase rectifier arrangement (1) of semiconductor valves (2), preferably a bridge rectifier circuit of diodes, wherein the rectifier arrangement (1) comprises a three-phase mains input (3) and a DC output (4), and at least one of the three phases (U, V, W) at the mains input (3) is connected to a first pole connection (A) of a three-pole circuit (5) for diverting an injection current (i_h3) into the three-pole circuit (5). It is provided in accordance with the invention that each phase (U, V, W) can respectively be connected with a switching element (S₁, S₂, S₃) to the first pole connection (A) of the three-pole circuit (5), and a second and third pole connection (B, C) of the three-pole circuit (5) is respectively connected to an output line (P_DC,N_DC) of the DC output (4) for control currents (i_cp,i_cn), wherein the three-pole circuit (5) comprises controllable semiconductor valves (S_cp+,S_cp−,S_cn+,S_cn−), preferably IGBTs, for the active control of the control currents (i_cp,i_cn) and/or the injection current (i_h3), and at least one choke (7) is arranged on one of the output lines (P_DC,N_DC) at the DC output (4), and a time-variable load (6) is provided at the DC output (4).

Claims

1. A rectifier circuit with a three-phase rectifier arrangement (1) of semiconductor valves (2), preferably a bridge rectifier circuit of diodes, wherein the rectifier arrangement (1) comprises a three-phase mains input (3) and a DC output (4), and at least one of the three phases (U, V, W) at the mains input (3) is connected to a first pole connection (A) of a three-pole circuit (5) for diverting an injection current (i_h3) into the three-pole circuit (5), wherein each phase (U, V, W) can respectively be connected with a switching element (S₁, S₂, S₃) to the first pole connection (A) of the three-pole circuit (5), and a second and third pole connection (B, C) of the three-pole circuit (5) is respectively connected to an output line (P_DC,N_DC) of the DC output (4) for control currents (i_cp,i_cn), wherein the three-pole circuit (5) comprises controllable semiconductor valves (S_cp+,S_cp−

,S_cn+,S_cn−

), preferably IGBTs, for the active control of the control currents (i_cp,i_cn) and/or the injection current (i_h3), and at least one choke (7) is arranged on one of the output lines (P_DC,N_DC) at the DC output (4), and a time-variable load (6) is provided at the DC output (4).

2. The rectifier circuit according to claim 1, wherein the second and third pole connection (B, C) of the three-pole circuit (5) are respectively connected via a second and third inductor (L_cp,L_cn) to one of the two output lines (P_DC,N_DC) of the DC output (4), and the choke (7) is provided between the second and third pole connection (B, C) and the load (6).

3. The rectifier circuit according to claim 2, wherein the first pole connection (A) is connected to the switching elements (S1, S2, S3) via a first inductor (L_h3), wherein the three inductors (L_h3,L_cp,L_cn) are arranged by means of a three-leg choke.

4. The rectifier circuit according to claim 1, wherein the two output lines (P_PD,N_DC) at the DC output (4) are connected to an output capacitor (C₀).

5. The rectifier circuit according to claim 1, wherein each of the three phases (U, V, W) at the mains input (3) is respectively connected to a filter capacitor (C_F), wherein the filter capacitors (C_F) are interconnected in a point-to-point manner in a star point (M_CF).

6. The rectifier circuit according to claim 1, wherein the three-pole circuit (5) is connected via at least one bypass capacitor (C_BF) to the mains input (3).

7. The rectifier circuit according to claim 1, wherein the three-pole circuit comprises three converter systems (9, 10, 11) with controllable semiconductor valves (S_cp+,S_cp−

,S_cn+,S_cn−

) and/or a bidirectional switch (S_h3), preferably arranged in a bridge structure, wherein the first pole connection (A) of the three-pole circuit (5) is provided on a first converter system (9), the second pole connection (B) of the three-pole circuit (5) on a second converter system (10), and the third pole connection (C) of the three-pole circuit (5) on a third converter system (11), and a connection to a branching point, i.e. a common cell center point (M) of the three-pole circuit (5), is provided from all three converter systems (9, 10, 11).

8. The rectifier circuit according to claim 7, wherein the first converter system (9) is provided as a three-level bridge leg, wherein the second and third converter system (10, 11) are provided as a half-bridge, and the three converter systems (9, 10, 11) are arranged by means of three branches (Z₁, Z₂, Z₃) which are switched in parallel and are provided with electronic components, wherein the first pole connection (A) of the three-pole circuit (5) is arranged on a first branch (Z₁), and the second and third pole connection (B, C) are arranged on a third branch (Z₃), and each of the branches (Z₁, Z₂, Z₃) comprises a center point connection (M₁, M₂, M₃), wherein the components of the branches (Z₁, Z₂, Z₃) are arranged symmetrically around said center point connections (M₁, M₂, M₃), and wherein a first center point connection (M₁) of the first branch (Z₁) is connected via a bidirectional switch (S_h3) to a second center point connection (M₂) of the second branch (Z₂), and the second center point connection (M₂) is directly conductively connected to a third center point connection (M₃) of the third branch (Z₃), wherein the third center point connection (M₃) is provided as the center point (M) of the three-pole circuit (5).

9. The rectifier circuit according to claim 1, wherein the three-pole circuit comprises two converter systems (10, 11) with controllable semiconductor valves (S_cp+,S_cp−

,S_cn+,S_cn−

), preferably arranged in a bridge structure, wherein the second pole connection (B) of the three-pole circuit (5) is provided on a second converter system (10), and the third pole connection (C) of the three-pole circuit (5) is provided on a third converter system (11), and a connection to a branching point, i.e. a common center point (5) of the three-pole circuit (5), is provided from both converter systems (10, 11), and the centres center point (M) is connected to the first pole connection (A).

10. The rectifier circuit according to claim 9, wherein the second and third converter system (10, 11) are provided as a half-bridge, wherein the two converter systems (10, 11) are arranged by means of two branches (Z₂, Z₃) switched in parallel, and the first pole connection (A) of the three-pole circuit (5) is connected to a second branch (Z₂), and the second and third pole connection (A, B) are arranged on a third branch (Z₃), and each of the branches (Z₂, Z₃) comprises a center point connection (M₂, M₃), wherein the components of the branches (Z₂, Z₃) are arranged symmetrically around said center point connections (M₂, M₃), and a second center point connection (M₂) of the second branch (Z₂) is directly conductively connected to a third center point connection (M₃) of the third branch (Z₃), wherein the third center point connection (M₃) is provided as the center point (M) of the three-pole circuit (5).

11. The rectifier circuit according to claim 10, wherein the second center point connection (M₂) is connected via a voltage source (U_x) to the first pole connection (A).

12. The rectifier circuit according to claim 8, wherein two bridge valves (D_h3+,D_h3−

), preferably diodes, are switched in the first branch (Z₁) in series with the same conducting direction, wherein the first center point connection (M₁) is arranged between the two bridge valves (D_h3+,D_h3−

).

13. The rectifier circuit according to claim 8, wherein two buffer capacitors (C_CP, C_CN) are switched in series on the second branch (Z₂), wherein the second center point connection (M₂) is arranged between the two buffer capacitors (C_CP, C_CN).

14. The rectifier circuit according to claim 8, wherein the four controllable semiconductor valves (S_cp+,S_cp−

,S_cn+,S_cn−

) are provided to be switched in series on the third branch (Z₃), wherein the center point (M) of the three-pole circuit (5) is arranged in the connection between two pairs of the controllable semiconductor valves (S_cp+,S_cp−

,S_cn+,S_cn−

) which are switched in series, and the second pole connection (B) is provided between the controllable semiconductor valves (S_cp+,S_cp−

) of the first pair, and the third pole connection (C) is provided between the controllable semiconductor valves (S_cn+,S_cn−

) of the second pair.

15. The rectifier circuit according to claim 12, at wherein the two bridge valves (D_h3+,D_h3−

) are arranged as controllable semiconductor valves (S_h3+, S_h3−

), preferably IGBTs.

16. The rectifier circuit according to claim 9, wherein the second and third converter system (10, 11) of the three-pole circuit (5) are arranged with known bidirectional three-level bridge legs, preferably two so-called three-level neutral-point-clamped-converters (3L-NPC), wherein the three-level bridge legs are arranged symmetrically around a center point branch (Zm) which is switched in parallel to the three-level bridge legs, and the center point branch (Zm) is arranged as two buffer capacitors (C_CP,C_CN) which are switched in series, and the center point (M) is provided between the two buffer capacitors (C_CP,C_CN), and a neutral connection (N₈) of the three-level bridge leg is connected to the center point (M) and the first pole connection (A), and an AC voltage connection (AC₈) of the three-level bridge leg is respectively provided as the second pole connection (B) and third pole connection (C) of the three-pole circuit (5).

17. The rectifier circuit according to claim 9, wherein the three-pole circuit (5) is connected with the first pole connection (A) to one respective side of two injection capacitors (C_h3p, C_h3n), which connection forms the center point (M) of the three-pole circuit (5), wherein the two other sides of the injection capacitors (C_h3p, C_h3n) are connected via a voltage source (U_x) and form connection points (M_P, M_N), wherein a current loop is provided which originates from the connection points (M_P,M_N) and comprises one respective buffer capacitor (C_CP, C_CN) and one respective pair of controllable semiconductor valves (S_cp+, S_cp−

,S_cn+,S_cn−

), and the second pole connection (B) and the third pole connection (C) are provided between the respective two controllable semiconductor valves (S_cp+,S_cp−

,S_cn+,S_cn−

) of a pair.

18. A method for impressing control currents (i_cp,i_cn) into a DC output (4) of a rectifier circuit with a three-phase rectifier arrangement (1) of semiconductor valves (2), preferably a three-pole bridge rectifier circuit of diodes, wherein an injection current (i_h3) is diverted from at least one of the three phases (U, V, W) at a mains input (3) of the rectifier circuit, wherein the injection current (i_h3) is supplied to a first pole connection (A) of a three-pole circuit (5), and the control of the injection current (i_h3) and/or the control currents (i_cp,i_cn) occurs by means of active components, preferably controllable semiconductor valves (S_cp+,S_cp−

,S_cn+,S_cn−

), in the three-pole circuit (5), and the rectifier currents (i_p,i_n) in two DC output lines (P_DC,N_DC) are added the control currents (i_cn,i_cp) via a second and third pole connection (B, C) of the three-pole circuit (5), and are guided at least through one choke (7) arranged on the DC output (4).

19. The method for impressing control currents (i_cp,i_cn) according to claim 18, wherein the injection current (i_h3) and/or the control currents (i_cp,i_cn) are conducted through at least two of three inductors (L_h3,L_cp,L_cn), provided on at least two of the three pole connections for smoothing and controlling the currents (i_h3,i_cn,i_cn) by differential voltages (U_L3,U_Ln,U_Lp) via the inductors (L_h3,L_cp,L_cn), and the third current (i_h3,i_cn,i_cp) is set by means of control of two of the three currents (i_h3,i_cn,i_cp).

20. The method for impressing control currents (i_cp,i_cn) according to claim 18 with a rectifier circuit, wherein a center point voltage (U_MN) is measured between the center point (M) of the three-pole circuit (5) and a neutral point (N), and a mean value of the center point voltage (U_MN) is controlled by one of the converter systems (9, 10, 11).

21. The method for impressing control currents (i_cp,i_cn) according to claim 20, wherein the mean value of the center point voltage (U_MN) is controlled to zero.

22. The method for impressing control currents (i_cp,i_cn) according to claim 20, wherein a first buffer capacitor voltage (U_CP) at the buffer capacitor (C_CP) is controlled to be greater than a voltage of the positive output line (P_DC) against a neutral point (N), and a second buffer capacitor voltage (U_CN) at the buffer capacitor (C_CN) is controlled to be lower than a voltage of the negative output line (N_DC) against the neutral point (N).

23. The method for impressing control currents (i_cp,i_cn) according to claim 20, wherein the control of the mean value of the center point voltage (U_MN) occurs by means of the controllable semiconductor valves (S_cp+,S_cp−

,S_cn+,S_cn−

, S_h3+,S_h3−

).

24. The method for impressing control currents (i_cp,i_cn) according to claim 19, wherein a first buffer capacitor voltage (U_CP) is minimized at the buffer capacitor (C_CP) and a second buffer capacitor voltage (U_CN) is minimized at the buffer capacitor (C_CN), wherein the center point voltage (U_MN) is controlled to the negative half value of an injection voltage (U_h3), and the injection voltage (U_h3) is applied between the first pole connection (A) and the neutral point (N).

25. The method for impressing control currents (i_cp,i_cn) according to claim 19, wherein the potential of the center point voltage (U_MN) is increased or decreased in relation to one of the two output lines (P_DC,N_DC) by means of the control of the voltage source (U_x).