Circuit and System of Using Junction Diode of MOS as Program Selector for Programmable Resistive Devices
First Claim
1. A programmable resistive device (PRD) memory comprising:
- a plurality of PRD cells, at least one of the PRD cells including at least;
at least one programmable resistive element (PRE) coupled to a first supply voltage line; and
at least one Metal-Oxide-Semiconductor (MOS) device having a source coupled to the PRE, a bulk coupled to a drain, the drain coupled to a second supply voltage line, and a gate coupled to a third supply voltage line,wherein the PRE is configured to be programmable by applying voltages to the first, second, and/or third supply voltage lines to turn on the source junction diode or a channel of the MOS to thereby change the PRE into a different logic state.
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Accused Products
Abstract
A programmable resistive device cell using at least one MOS device as selector can be programmed or read by turning on a source junction diode of the MOS or a channel of the MOS. A programmable resistive device cell can include at least one programmable resistive element and at least one MOS device. The programmable resistive element can be coupled to a first supply voltage line. The MOS can have a source coupled to the programmable resistive element, a bulk coupled to a drain, a drain coupled to a second supply voltage line, and a gate coupled to a third supply voltage line. The programmable resistive element can be configured to be programmable or readable by applying voltages to the first, second, and/or third supply voltage lines to turn on the source junction of the MOS and/or to turn on the channel of the MOS.
47 Citations
21 Claims
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1. A programmable resistive device (PRD) memory comprising:
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a plurality of PRD cells, at least one of the PRD cells including at least; at least one programmable resistive element (PRE) coupled to a first supply voltage line; and at least one Metal-Oxide-Semiconductor (MOS) device having a source coupled to the PRE, a bulk coupled to a drain, the drain coupled to a second supply voltage line, and a gate coupled to a third supply voltage line, wherein the PRE is configured to be programmable by applying voltages to the first, second, and/or third supply voltage lines to turn on the source junction diode or a channel of the MOS to thereby change the PRE into a different logic state. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14)
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15. An electronic system, comprising:
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a processor; and a programmable resistive device memory operatively connected to the processor, the programmable resistive device memory including a plurality of programmable resistive device (PRD) cells, at least one of the PRD cells comprising; a programmable resistive element (PRE) coupled to a first supply voltage line; and at least one Metal-Oxide-Semiconductor (MOS) device having a source coupled to the PRE, a bulk coupled to a drain, the drain coupled to a second supply voltage line, and a gate coupled to a third supply voltage line, wherein the PRE is configured to be programmable by applying voltages to the first, second, and/or third supply voltage lines to turn on the source junction diode or a channel of the MOS to thereby change the PRE into a different logic state, and wherein the PRE is configured to be readable by applying voltages to the first, second, and/or third supply voltage lines to turn on the source junction diode or the channel of the MOS to thereby read the PRE resistance into a logic state. - View Dependent Claims (16, 17)
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18. A method for operating a programmable resistive device memory, the method comprising:
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providing a plurality of programmable resistive device cells, at least one of the programmable resistive device cells includes at least (i) a programmable resistive element coupled to a first supply voltage line; and
(ii) at least one Metal-Oxide-Semiconductor (MOS) device as a selector having a source coupled to the programmable resistive element, a bulk coupled to a drain, the drain coupled to a second supply voltage line, and a gate coupled to a third supply voltage line;programming a logic state into at least one of the programmable resistive device cells by applying voltages to the first, the second, and/or the third supply voltage lines to turn on the source junction diode or the channel of the MOS; and sensing a current flowing in one of the at least one programmable resistive device cells by applying voltages to the first, second and/or the third supply voltage lines to turn on the source junction diode or the channel of the MOS. - View Dependent Claims (19, 20, 21)
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Specification