METHOD OF SECURE MANAGEMENT OF A MEMORY SPACE FOR MICROCONTROLLER

• US 20150032976A1
• Filed: 04/04/2013
• Published: 01/29/2015
• Est. Priority Date: 04/18/2012
• Status: Active Grant

• Current Assignee: Schneider Electric Industries SAS (Schneider Electric SE)
• Original Assignee: Schneider Electric Industries SAS (Schneider Electric SE)
• Inventors: Chapier, Pascal, Jaraudias, Patrice
• Granted Patent: US 9,703,727 B2
• Time in Patent Office: Days
• US Class Current: 711/152
• CPC Class Codes: G06F 12/1036 for multiple virtual address spaces, e.g. segmentation G06F12/1045 takes precedence
• CPC Class Codes: G06F 12/145 the protection being virtual, e.g. for virtual blocks or segments before a translation mechanism
• CPC Class Codes: G06F 12/1491 in a hierarchical protection system, e.g. privilege levels, memory rings
• CPC Class Codes: G06F 21/64 Protecting data integrity, e.g. using checksums, certificates or signatures
• CPC Class Codes: G06F 21/74 operating in dual or compartmented mode, i.e. at least one secure mode
• CPC Class Codes: G06F 21/79 in semiconductor storage media, e.g. directly-addressable memories
• CPC Class Codes: G06F 2221/2147 Locking files

Abstract

A method of managing an electronic microcontroller system, the microcontroller system including: two processors with a first processor configured for execution of a nonsecure application exhibiting a nonguaranteed level of functional security and integrity, and a second processor dedicated to execution of a secure application implementing code and data, and involving a guaranteed level of functional security and integrity, the secure application to implement a security function; and a mechanism to access to a shared memory space. The first processor includes a unit for managing the memory configured to implement a write access control, to manage write access to the shared memory space, that is not modifiable when the secure application implements its security function.

Claims

1-4. -4. (canceled)

5. A method of management of an electronic microcontroller system, the microcontroller system including:

first and second processors, the first processor configured for execution of a non-secure application, exhibiting a non-guaranteed level of functional security and integrity, and a second processor dedicated to execution of a secure application, implementing code and data, and involving a guaranteed level of functional security and integrity, the secure application able to implement a security function; and

means of access to a shared memory space;

the first processor including a memory management unit configured to implement a check of write-access, to manage write-access to the shared memory space, to be non-modifiable when the secure application implements its security function,

the management method ensuring check of write-access rendered non-modifiable and comprising;

apportionment of the shared memory space between a memory area allocated to the secure application and a memory area allocated to the non-secure application;

implementation of a buffer for anticipation of a translation of the addresses;

loading into the buffer for anticipation of the translation of the addresses of a set of rules of access to the shared memory space including a rule prohibiting writing by the non-secure application in a reserved area of the memory area allocated to the secure application, the execution of the rule prohibiting writing being checked by the secure application;

copying into the shared memory space of an image of the buffer for the anticipation of the translation of the addresses;

loading into the image of the buffer for the anticipation of the translation of the addresses of a rule prohibiting writing in the buffer for the anticipation of the translation of the images;

implementation, by the memory management unit, of access rules contained in the image of the buffer for the anticipation of the translation of the addresses.

6. The method as claimed in claim 5, further comprising verification of integrity of the buffer for the anticipation of the translation of the addresses and of integrity of the code and of the data corresponding to the secure application.

7. The method as claimed in claim 5, further comprising constructing a security CRC (cyclic redundancy check) configured to detect errors of transmission or of transfer, the CRC being associated with the buffer for the anticipation of the translation of the addresses.

8. The method as claimed in claim 5, further comprising, after each operation, verifying a proper progress of a previous operation.