PROVIDING QUEUE BARRIERS WHEN UNSUPPORTED BY AN I/O PROTOCOL OR TARGET DEVICE

• US 20150033234A1
• Filed: 07/22/2014
• Published: 01/29/2015
• Est. Priority Date: 07/23/2013
• Status: Abandoned Application

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Qualcomm, Inc.
• Inventors: Shacham, Assaf, Lanel, Itai, Haim (Erez), Maya
• Application Number:
  US14/338,235
• Publication Number:
  US 20150033234A1
• Time in Patent Office: Days
• US Class Current: 718/102
• CPC Class Codes: G06F 9/4843 by program, e.g. task dispatcher, supervisor, operating system
• CPC Class Codes: G06F 9/522 Barrier synchronisation

Abstract

A host controller is provided that unilaterally supports queue barrier functionality. The host controller may receive a first task marked with a queue barrier indicator. As a result, the host controller stalls transmission of the first task to a target device. Additionally, the host controller also stalls transmission of any task, occurring after the first task, to the target device. The host controller only sends the first task to the target device once an indication is received from the target device that all previously sent tasks have been processed. The host controller only sends any task, occurring after the first task, to the target device once an indication is received from the target device that the first task has been processed.

Claims

1. A host controller, comprising:

a communication interface to communicate with a target device;

a processing circuit coupled to the communication interface, the processing circuit adapted to;

obtain a first task marked with a queue barrier indicator;

stall transmission of the first task to the target device;

send the first task to the target device once an indication is received from the target device that all previously sent tasks have been processed.

2. The host controller of claim 1, wherein the processing circuit is further adapted to:

sequentially obtain multiple tasks from a task queue, wherein the first task is among the multiple tasks;

ascertain whether each task is marked with a queue barrier indicator; and

determine that the first task is marked with the queue barrier indicator.

3. The host controller of claim 1, wherein the processing circuit is further adapted to:

stall transmission of any task, occurring after the first task, to the target device until the indication is received from the target device that all previously sent tasks have been processed.

4. The host controller of claim 3, wherein the processing circuit is further adapted to:

send any task, occurring after the first task, to the target device once an indication is received from the target device that the first task has been processed.

5. The host controller of claim 1, wherein the host controller and target device communicate using a protocol in which queue barrier indicator functionality is unsupported.

6. The host controller of claim 1, wherein a separate queue barrier indicator functionality is unsupported in the target device.

7. The host controller of claim 1, wherein the queue barrier indicator is distinct from a separate queue barrier functionality supported in the target device or an input/output communication protocol between the host controller and target device.

8. The host controller of claim 1, wherein the host controller is a separate device from the target device.

9. The host controller of claim 1, wherein the host controller is integrated with the target device in a single semiconductor device.

10. The host controller of claim 1, wherein the target device is a storage device and the tasks include read and/or write operations.

11. The host controller of claim 1, wherein the first task is sent to the target device without the queue barrier indicator.

12. The host controller of claim 1, wherein the first task and other tasks are obtained by the processing circuit from a task queue, and each of the first task and other tasks are processed by the processing circuit in the order in which each task is placed in the task queue relative to other tasks marked with a queue barrier indicator.

13. A method operational on a host controller for communicating with a target device, comprising:

obtaining a first task marked with a queue barrier indicator;

stalling transmission of the first task to the target device;

sending the first task to the target device once an indication is received from the target device that all previously sent tasks have been processed.

14. The method of claim 13, further comprising:

sequentially obtaining multiple tasks from a task queue, wherein the first task is among the multiple tasks;

ascertaining whether each task is marked with a queue barrier indicator; and

determining that the first task is marked with the queue barrier indicator.

15. The method of claim 14, further comprising:

stalling transmission of any task, occurring after the first task, to the target device until the indication is received from the target device that all previously sent tasks have been processed.

16. The method of claim 15, further comprising:

sending any task, occurring after the first task, to the target device once an indication is received from the target device that the first task has been processed.

17. The method of claim 13, wherein the host controller and target device communicate using a protocol in which queue barrier indicator functionality is unsupported.

18. The method of claim 13, wherein the queue barrier indicator is distinct from a separate queue barrier functionality supported in the target device or an input/output communication protocol between the host controller and target device.

19. The method of claim 13, wherein queue barrier indicator functionality is unsupported in the target device.

20. A non-transitory processor-readable storage medium having one or more instructions which, when executed by at least one processing circuit, cause the at least one processing circuit to:

obtain a first task marked with a queue barrier indicator;

stall transmission of the first task to the target device;

send the first task to the target device once an indication is received from the target device that all previously sent tasks have been processed.

21. The non-transitory processor-readable storage medium of claim 20, further having one or more instructions which, when executed by at least one processing circuit, cause the at least one processing circuit to:

sequentially obtain multiple tasks from a task queue, wherein the first task is among the multiple tasks;

ascertain whether each task is marked with a queue barrier indicator; and

determine that the first task is marked with the queue barrier indicator.

22. The non-transitory processor-readable storage medium of claim 20, further having one or more instructions which, when executed by at least one processing circuit, cause the at least one processing circuit to:

stall transmission of any task, occurring after the first task, to the target device until the indication is received from the target device that all previously sent tasks have been processed.

23. The non-transitory processor-readable storage medium of claim 20, further having one or more instructions which, when executed by at least one processing circuit, cause the at least one processing circuit to:

send any task, occurring after the first task, to the target device once an indication is received from the target device that the first task has been processed.