Super Junction Semiconductor Device and Manufacturing Method

• US 20150035002A1
• Filed: 07/31/2013
• Published: 02/05/2015
• Est. Priority Date: 07/31/2013
• Status: Abandoned Application

• Current Assignee: Infineon Technologies Austria Ag (Infineon Technologies AG)
• Original Assignee: Infineon Technologies Austria Ag (Infineon Technologies AG)
• Inventors: Weber, Hans
• Application Number:
  US13/955,894
• Publication Number:
  US 20150035002A1
• Time in Patent Office: Days
• US Class Current: 257/139
• CPC Class Codes: H01L 21/3063 Electrolytic etching
• CPC Class Codes: H01L 29/0634 Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/66333 Vertical insulated gate bipolar transistors
• CPC Class Codes: H01L 29/6634 with a recess formed by etching in the source/emitter contact region H01L29/66348 takes precedence; etching of semiconductor bodies H01L21/302
• CPC Class Codes: H01L 29/66348 with a recessed gate
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7395 Vertical transistors, e.g. vertical IGBT
• CPC Class Codes: H01L 29/7397 and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A method for manufacturing a super junction semiconductor device includes forming a trench in an n-doped semiconductor body and forming a first p-doped semiconductor layer lining sidewalls and a bottom side of the trench. The method further includes removing a part of the first p-doped semiconductor layer at the sidewalls and at the bottom side of the trench by electrochemical etching, and filling the trench.

Claims

1. A method for manufacturing a super junction semiconductor device, the method comprising:

forming a trench in a semiconductor body of a first conductivity type;

forming a first semiconductor layer of a second conductivity type other than the first conductivity type lining sidewalls and a bottom side of the trench;

removing a part of the first semiconductor layer at the side walls and at the bottom side of the trench by electrochemical etching; and

filling the trench.

2. The method of claim 1, wherein removing the part of the first semiconductor layer includes alkaline wet etching of the first semiconductor layer by applying a blocking voltage between an alkaline solution in contact with the first semiconductor layer and with the semiconductor body.

3. The method of claim 1, further comprising, before electrochemical etching,

forming a highly doped region of the first conductivity type in the first semiconductor layer outside the trench by introducing dopants of the first conductivity type in the first semiconductor layer, the highly doped region being configured to electrically couple the first semiconductor layer and an alkaline solution during electrochemical etching.

4. The method of claim 1, wherein forming the first semiconductor layer includes forming a first sub-layer of the second conductivity type, and, thereafter, forming a second sub-layer of the second conductivity type, wherein an averaged doping concentration of the first sub-layer is higher than an averaged doping concentration of the second sub-layer.

5. The method of claim 4, wherein the averaged doping concentration of the first sub-layer ranges between 5×

10¹⁵ cm<sup>−

3</sup> and 5×

10¹⁷ cm<sup>−

3</sup> and the averaged doping concentration of the second sub-layer ranges between 1×

10¹⁵ cm-3 and 5×

10¹⁶ cm<sup>−

3</sup>.

6. The method of claim 1, further comprising:

forming a source electrode and a gate electrode at a first side of the semiconductor body; and

forming a drain electrode at a second side of the semiconductor body opposite to the first side.

7. The method of claim 1, wherein filling the trench includes at least one of forming an intrinsic or a lightly doped semiconductor material in the trench and forming a dielectric material in the trench.

8. The method of claim 1, wherein filling the trench includes filling the trench with a material including a void.

9. The method of claim 1, wherein after forming the trench and before forming the first semiconductor layer, the method further comprises:

forming a third semiconductor layer of the second conductivity type the lining sidewalls and the bottom side of the trench;

removing the third semiconductor layer from the bottom side of the trench; and

forming a fourth semiconductor layer of the first conductivity type lining the sidewalls and the bottom side of the trench.

10. The method of claim 9, wherein forming the third semiconductor layer, removing the third semiconductor layer from the bottom side of the trench and forming the fourth semiconductor layer are performed several times.

11. A super junction semiconductor device, comprising:

a super junction structure including a first U-shaped semiconductor layer of a second conductivity type having opposite sidewalls and a bottom side, wherein each one of the opposite sidewalls of the first U-shaped semiconductor layer adjoins a compensation region of a complementary first conductivity type and the bottom side of the first U-shaped semiconductor layer adjoins a semiconductor body portion of the first conductivity type; and

a filling material filling an inner area of the first U-shaped semiconductor layer,

wherein the filling material is an intrinsic or a lightly doped semiconductor material.

13. The super junction semiconductor device of claim 11, wherein the filling material includes a void.

14. The super junction semiconductor device of claim 11, wherein the super junction semiconductor device is a vertical insulated gate field effect transistor (IGBT) including a first load terminal and a control terminal at a first side of a semiconductor body and a second load terminal at a second side of the semiconductor body opposite to the first side.

12. (canceled)

15. A super junction semiconductor device, comprising:

a super junction structure including a first U-shaped semiconductor layer of a second conductivity type;

a filling material filling an inner area of the first U-shaped semiconductor layer; and

a compensation region of a complementary first conductivity type, wherein

at least one pair of a semiconductor region of the first conductivity type and a semiconductor region of the second conductivity type is arranged between the first U-shaped semiconductor layer and the compensation region.

16. The super junction semiconductor device of claim 15, wherein a width of the compensation region is greater than a width of the semiconductor region of the first conductivity type.

17. The super junction semiconductor device of claim 15, wherein an averaged doping concentration of the compensation region is smaller than an averaged doping concentration of the semiconductor region of the first conductivity type.

18. The super junction semiconductor device of claim 15, wherein the filling material is at least one of an intrinsic or a lightly doped semiconductor material and a dielectric material.

19. The super junction semiconductor device of claim 15, wherein the filling material includes a void.

20. The super junction semiconductor device of claim 15, wherein the super junction semiconductor device is a vertical insulated gate field effect transistor (IGBT) including a first load terminal and a control terminal at a first side of a semiconductor body and a second load terminal at a second side of the semiconductor body opposite to the first side.