Split Gate Non-volatile Flash Memory Cell Having A Silicon-Metal Floating Gate And Method Of Making Same

• US 20150035040A1
• Filed: 08/02/2013
• Published: 02/05/2015
• Est. Priority Date: 08/02/2013
• Status: Active Grant

• Current Assignee: Silicon Storage Technology Incorporated (Microchip Technology Incorporated)
• Original Assignee: Silicon Storage Technology Incorporated (Microchip Technology Incorporated)
• Inventors: Yoo, Jong-Won, Kotov, Alexander, Tkachev, Yuri, Su, Chien-Sheng
• Granted Patent: US 9,123,822 B2
• Time in Patent Office: Days
• US Class Current: 257/320
• CPC Class Codes: H01L 29/40114 the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
• CPC Class Codes: H01L 29/42328 with at least one additional gate other than the floating gate and the control gate, e.g. program gate, erase gate or select gate
• CPC Class Codes: H01L 29/66825 with a floating gate H01L29/6684 takes precedence
• CPC Class Codes: H01L 29/788 with floating gate H01L29/78391 takes precedence
• CPC Class Codes: H01L 29/7881 Programmable transistors with only two possible levels of programmation H01L29/7888 takes precedence
• CPC Class Codes: H01L 29/7883 charging by tunnelling of carriers, e.g. Fowler-Nordheim tunnelling
• CPC Class Codes: H10B 41/30 characterised by the memory core region

Abstract

A non-volatile memory cell includes a substrate of a first conductivity type with first and second spaced apart regions of a second conductivity type, forming a channel region therebetween. A select gate is insulated from and disposed over a first portion of the channel region which is adjacent to the first region. A floating gate is insulated from and disposed over a second portion of the channel region which is adjacent the second region. Metal material is formed in contact with the floating gate. A control gate is insulated from and disposed over the floating gate. An erase gate includes a first portion insulated from and disposed over the second region and is insulated from and disposed laterally adjacent to the floating gate, and a second portion insulated from and laterally adjacent to the control gate and partially extends over and vertically overlaps the floating gate.

Claims

1. A non-volatile memory cell comprising:

a substrate of a first conductivity type, having a first region of a second conductivity type, a second region of the second conductivity type spaced apart from the first region, forming a channel region therebetween;

a select gate insulated from and disposed over a first portion of the channel region which is adjacent to the first region;

a floating gate insulated from and disposed over a second portion of the channel region which is adjacent the second region;

metal material formed in contact with the floating gate;

a control gate insulated from and disposed over the floating gate;

an erase gate that includes first and second portions, wherein;

the first portion is insulated from and disposed over the second region, and is insulated from and disposed laterally adjacent to the floating gate; and

the second portion is insulated from and laterally adjacent to the control gate, and partially extends over and vertically overlaps the floating gate.

2. The memory cell of claim 1, wherein the metal material is disposed as a layer on a top surface of the floating gate.

3. The memory cell of claim 2, wherein the layer of the metal material extends over the entire top surface of the floating gate.

4. The memory cell of claim 2, wherein the layer of the metal material extends over only a portion of the top surface of the floating gate, wherein the layer of the metal material does not extend over any portion of the top surface over which the erase gate second portion extends.

5. The memory cell of claim 1, wherein:

the floating gate comprises two discrete layers of polysilicon material, and the metal material is disposed as a layer between the two discrete layers of polysilicon material.

6. The memory cell of claim 1, wherein the metal material is formed as a spacer of the metal material along a side surface of the floating gate.

7. A method of forming a non-volatile memory cell comprising:

forming, in a substrate of a first conductivity type, spaced apart first and second regions of a second conductivity type, defining a channel region therebetween;

forming a select gate insulated from and disposed over a first portion of the channel region which is adjacent to the first region;

forming a floating gate insulated from and disposed over a second portion of the channel region which is adjacent the second region;

forming metal material in contact with the floating gate;

forming a control gate insulated from and disposed over the floating gate;

forming an erase gate that includes first and second portions, wherein;

the first portion is insulated from and disposed over the second region, and is insulated from and disposed laterally adjacent to the floating gate; and

the second portion is insulated from and laterally adjacent to the control gate, and partially extends over and vertically overlaps the floating gate.

8. The method of claim 7, wherein the metal material is formed as a layer on a top surface of the floating gate.

9. The method of claim 8, wherein the layer of the metal material extends over the entire top surface of the floating gate.

10. The method of claim 8, wherein the layer of the metal material extends over only a portion of the top surface of the floating gate, wherein the layer of the metal material does not extend over any portion of the top surface over which the erase gate second portion extends.

11. The method of claim 7, wherein:

the floating gate comprises two discrete layers of polysilicon material, and

the metal material is formed as a layer disposed between the two discrete layers of polysilicon material.

12. The method of claim 7, wherein the metal material is formed as a spacer of the metal material along a side surface of the floating gate.

13. The method of claim 7, wherein a portion of the floating gate is insulated from and disposed over a portion of the second region.

14. The method of claim 7 wherein the select gate and the erase gate are formed in a same processing step.

15. The method of claim 7 wherein the first region is formed after the control gate and the floating gate are formed.

16. The method of claim 7 wherein said second region is formed after the select gate and erase gate are formed.