Dual Trench Rectifier and Method for Forming the Same

• US 20150035047A1
• Filed: 08/01/2013
• Published: 02/05/2015
• Est. Priority Date: 08/01/2013
• Status: Active Grant

• Current Assignee: Qinhai Jin
• Original Assignee: Chip Integration Tech. Co., Ltd.
• Inventors: Jin, Qinhai
• Granted Patent: US 9,117,902 B2
• Time in Patent Office: Days
• US Class Current: 257/328
• CPC Class Codes: H01L 27/0814 Diodes only
• CPC Class Codes: H01L 29/0607 for preventing surface leakage or controlling electric field concentration
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/45 Ohmic electrodes
• CPC Class Codes: H01L 29/47 Schottky barrier electrodes H01L29/435 takes precedence
• CPC Class Codes: H01L 29/66136 PN junction diodes
• CPC Class Codes: H01L 29/7827 Vertical transistors H01L29/7802, H01L29/78642 take precedence
• CPC Class Codes: H01L 29/8613 Mesa PN junction diodes
• CPC Class Codes: H01L 29/8725 of the trench MOS barrier type [TMBS]

Abstract

A structure of dual trench rectifier comprises of the following elements. A plurality of trenches are formed parallel in an n− epitaxial layer on an n+ semiconductor substrate and spaced with each other by a mesa. A plurality of recesses are formed on the mesas. Each the trench has a trench oxide layer formed on the sidewalls and bottom thereof, and a first poly silicon layer is filled therein to form MOS structures. Each the recess has a recess oxide layer formed on the sidewalls and bottom thereof, and a second poly silicon layer is filled therein to form MOS structures. A plurality of p type bodies are formed at two sides of the MOS structures in recesses. A top metal is formed above the semiconductor substrate for serving as an anode. A bottom metal is formed beneath the semiconductor substrate for serving as a cathode.

Claims

1. A dual trench rectifier comprising of:

a plurality of trenches formed parallel in an n−

epitaxial layer on a heavy doped n+ semiconductor substrate, wherein each the trench has a trench oxide layer formed on a bottom and sidewalls thereof;

a plurality of recesses formed in the n−

epitaxial layer on mesas between the plurality of trenches, wherein each the recess has a recess oxide layer formed on a bottom and sidewalls thereof;

a first polysilicon layer with a conductive impurity formed in the plurality of trenches;

a second polysilicon layer with a conductive impurity formed in the plurality of recesses to form MOS structures, wherein each the MOS structure includes the second polysilicon layer, the recess oxide layer and the n−

epitaxial layer;

a plurality of p type bodies formed in the n−

epitaxial layer below the mesas at two sides of the plurality of recesses;

a top metal layer formed on top of the first and second polysilicon layers and p type bodies for serving as an anode, and a bottom metal layer formed beneath the heavy doped n+ semiconductor substrate for serving as a cathode.

2. The dual trench rectifier of claim 1, wherein each the p type body includes two n+ ion implanted areas individually adjacent to two sides of the MOS structures.

3. The dual trench rectifier of claim 1, further comprising a metal silicide formed on the second polysilicon layer and the n−

epitaxial layer to connect with the top metal layer.

4. A dual trench rectifier comprising of:

a plurality of trenches formed parallel in a n−

epitaxial layer on a heavy doped n+ semiconductor substrate, wherein each the trench has a trench oxide layer formed on a bottom and sidewalls thereof;

a plurality of recesses formed in the n−

epitaxial layer of mesas between the plurality of trenches, and a recess oxide layer formed on a bottom and sidewalls of each the recess and on the mesas adjacent to two sides of each the recess;

a first polysilicon layer with a conductive impurity formed in the plurality of trenches, wherein the recess oxide layer is also formed on the first polysilicon layer;

a second polysilicon layer with a conductive impurity, overfilled in the plurality of recesses to cover the mesas, being higher than the recess oxide layer on the first polysilicon layer of the plurality of trenches, wherein the second polysilicon layer is patterned to form a plurality of rows of MOS structures perpendicular to the plurality of trenches, and each the MOS structure includes the second polysilicon layer, the recess oxide layer and the n−

epitaxial layer;

a plurality of p type bodies formed in the n−

epitaxial layer below the mesas adjacent to the plurality of rows of MOS structures; and

a top metal layer formed on top of the plurality of rows of MOS structures and the plurality of p type bodies adjacent thereto for serving as an anode, and a bottom metal layer formed beneath the heavy doped n+ semiconductor substrate for serving as a cathode.

5. The dual trench rectifier of claim 4, wherein each the p type body includes two n+ ion implanted areas individually adjacent to two sides of the MOS structures.