A SUPPER JUNCTION STRUCTURE INCLUDES A THICKNESS OF FIRST AND SECOND SEMICONDUCTOR REGIONS GRADUALLY CHANGED FROM A TRANSISTOR AREA INTO A TERMINATION AREA
First Claim
1. A super junction semiconductor device, comprising:
- a super junction structure including first and second areas alternately arranged along a first lateral direction and extending in parallel along a second lateral direction;
each one of the first areas includes a first semiconductor region of a first conductivity type;
each one of the second areas includes, along the first lateral direction, an inner area between opposite second semiconductor regions of a second conductivity type opposite to the first conductivity type; and
whereina width w1 of the first of the first semiconductor region in a transistor cell area is greater than in an edge termination area, and a width w2 of each one of the second semiconductor regions in the transistor cell area is greater than in the edge termination area.
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Abstract
A super junction semiconductor device includes a super junction structure including first and second areas alternately arranged along a first lateral direction and extending in parallel along a second lateral direction. Each one of the first areas includes a first semiconductor region of a first conductivity type. Each one of the second areas includes, along the first lateral direction, an inner area between opposite second semiconductor regions of a second conductivity type opposite to the first conductivity type. A width w1 of the first of the first semiconductor region in a transistor cell area is greater than in an edge termination area, and a width w2 of each one of the second semiconductor regions in the transistor cell area is greater than in the edge termination area.
13 Citations
19 Claims
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1. A super junction semiconductor device, comprising:
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a super junction structure including first and second areas alternately arranged along a first lateral direction and extending in parallel along a second lateral direction;
each one of the first areas includes a first semiconductor region of a first conductivity type;
each one of the second areas includes, along the first lateral direction, an inner area between opposite second semiconductor regions of a second conductivity type opposite to the first conductivity type; and
whereina width w1 of the first of the first semiconductor region in a transistor cell area is greater than in an edge termination area, and a width w2 of each one of the second semiconductor regions in the transistor cell area is greater than in the edge termination area. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9. A super junction semiconductor device, comprising:
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a super junction structure including first and second areas alternately arranged along a first lateral direction and extending in parallel along a second lateral direction;
each one of the first areas includes a first semiconductor region of a first conductivity type;
each one of the second areas includes, along the first lateral direction, an inner area between opposite second semiconductor regions of a second conductivity type opposite to the first conductivity type; anda channel stopper structure including a doped semiconductor region electrically coupled to a field plate, wherein the second semiconductor regions extending along the second lateral direction from the transistor cell area through the edge termination area overlap with the field plate. - View Dependent Claims (10, 11, 12, 13, 14)
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15. A super junction semiconductor device, comprising:
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a super junction structure including first and second areas alternately arranged along a first lateral direction and extending in parallel along a second lateral direction;
each one of the first areas includes a first semiconductor region of a first conductivity type;
each one of the second areas includes, along the first lateral direction, an inner area between opposite second semiconductor regions of a second conductivity type opposite to the first conductivity type; anda transition area between the transistor cell area and the edge termination area, wherein a depth d2 of the second semiconductor regions in different ones of the second areas decreases, along the first lateral direction, from the transistor cell area into the transition area. - View Dependent Claims (16, 17, 18, 19)
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Specification