ENABLING ENHANCED RELIABILITY AND MOBILITY FOR REPLACEMENT GATE PLANAR AND FINFET STRUCTURES
First Claim
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1. A method for semiconductor fabrication, comprising:
- forming at least one of a diffusion barrier layer and a metal containing layer over a dielectric layer in a gate cavity;
performing a first anneal to diffuse elements from the at least one of the diffusion barrier layer and the metal containing layer into the dielectric layer;
removing the metal containing layer and the diffusion barrier layer; and
performing a second anneal to adjust diffusion of the elements in the dielectric layer to provide a gate dielectric region.
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Abstract
A method for semiconductor fabrication includes forming at least one of a diffusion barrier layer and a metal containing layer over a dielectric layer in a gate cavity. A first anneal is performed to diffuse elements from the at least one of the diffusion barrier layer and the metal containing layer into the dielectric layer. The metal containing layer and the diffusion barrier layer are removed. A second anneal is performed to adjust diffusion of the elements in the dielectric layer to provide a gate dielectric region.
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Citations
20 Claims
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1. A method for semiconductor fabrication, comprising:
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forming at least one of a diffusion barrier layer and a metal containing layer over a dielectric layer in a gate cavity; performing a first anneal to diffuse elements from the at least one of the diffusion barrier layer and the metal containing layer into the dielectric layer; removing the metal containing layer and the diffusion barrier layer; and performing a second anneal to adjust diffusion of the elements in the dielectric layer to provide a gate dielectric region. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11)
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12. A method for semiconductor fabrication, comprising:
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forming a dielectric layer in gate cavities associated with first and second device regions; forming a second diffusion barrier layer over a metal containing layer over the dielectric layer in the first device region, and a first diffusion barrier layer over the dielectric layer in the second device region; performing a first anneal to diffuse elements from the second diffusion barrier layer and the metal containing layer into the dielectric layer in the first device region, and from the first diffusion barrier into the dielectric layer in the second device region; removing the second diffusion barrier, the metal containing layer, and the first diffusion barrier; and performing a second anneal to adjust diffusion of the elements in the dielectric layer to provide a gate dielectric region. - View Dependent Claims (13, 14)
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15. A semiconductor device, comprising:
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a substrate having a plurality of regions including a first region and a second region; a first gate structure formed in the first region including a first dielectric layer, which has a top layer, middle layer, and bottom layer of the first dielectric layer, the top layer of the first dielectric layer including hafnium (Hf), lanthanum (La), oxygen (O), and nitrogen (N), the middle layer of the first dielectric layer including La, silicon (Si), O, and N, and the bottom layer of the first dielectric layer including undoped silicon dioxide; and a second gate structure formed in the second region including a second dielectric layer, which has a top layer, middle layer, and bottom layer of the second dielectric layer, the top layer of the second dielectric layer including Hf, O, and N, the middle layer of the second dielectric layer including Si, O, and N, and the bottom layer of the second dielectric layer including undoped silicon dioxide. - View Dependent Claims (16, 17, 18, 19, 20)
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Specification