ENABLING ENHANCED RELIABILITY AND MOBILITY FOR REPLACEMENT GATE PLANAR AND FINFET STRUCTURES

• US 20150035073A1
• Filed: 08/05/2013
• Published: 02/05/2015
• Est. Priority Date: 08/05/2013
• Status: Active Grant

• Current Assignee: GlobalFoundries, Inc.
• Original Assignee: GlobalFoundries, Inc., International Business Machines Corporation
• Inventors: Ando, Takashi, Cartier, Eduard A., Lai, Wing L., Narayanan, Vijay, Ramachandran, Ravikumar, Choi, Kisik
• Granted Patent: US 9,099,393 B2
• Time in Patent Office: Days
• US Class Current: 257/369
• CPC Class Codes: H01L 21/28185 with a treatment, e.g. annealing, after the formation of the gate insulator and before the formation of the definitive gate conductor
• CPC Class Codes: H01L 21/28229 by deposition of a layer, e.g. metal, metal compound or poysilicon, followed by transformation thereof into an insulating layer
• CPC Class Codes: H01L 21/823821 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 21/823842 gate conductors with different gate conductor materials or different gate conductor implants, e.g. dual gate structures
• CPC Class Codes: H01L 27/092 complementary MIS field-effect transistors
• CPC Class Codes: H01L 27/0924 including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/0649 Dielectric regions, e.g. SiO2 regions, air gaps
• CPC Class Codes: H01L 29/42364 characterised by the insulating layer, e.g. thickness or uniformity H01L29/42324 and H01L29/4234 take precedence
• CPC Class Codes: H01L 29/495 the conductor material next to the insulator being a simple metal, e.g. W, Mo H01L29/4908, H01L29/4983 take precedence
• CPC Class Codes: H01L 29/51 Insulating materials associated therewith for MIS structures on thin film semiconductor H01L29/4908
• CPC Class Codes: H01L 29/513 the variation being perpendicular to the channel plane
• CPC Class Codes: H01L 29/517 the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate H01L29/518 takes precedence
• CPC Class Codes: H01L 29/518 the insulating material containing nitrogen, e.g. nitride, oxynitride, nitrogen-doped material
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/7851 with the body tied to the substrate

Abstract

A method for semiconductor fabrication includes forming at least one of a diffusion barrier layer and a metal containing layer over a dielectric layer in a gate cavity. A first anneal is performed to diffuse elements from the at least one of the diffusion barrier layer and the metal containing layer into the dielectric layer. The metal containing layer and the diffusion barrier layer are removed. A second anneal is performed to adjust diffusion of the elements in the dielectric layer to provide a gate dielectric region.

Claims

1. A method for semiconductor fabrication, comprising:

forming at least one of a diffusion barrier layer and a metal containing layer over a dielectric layer in a gate cavity;

performing a first anneal to diffuse elements from the at least one of the diffusion barrier layer and the metal containing layer into the dielectric layer;

removing the metal containing layer and the diffusion barrier layer; and

performing a second anneal to adjust diffusion of the elements in the dielectric layer to provide a gate dielectric region.

2. The method as recited in claim 1, wherein forming includes:

forming a second diffusion barrier layer over the metal containing layer over the dielectric layer in a first device region; and

forming the diffusion barrier layer over the dielectric layer in a second device region.

3. The method as recited in claim 2, wherein performing the first anneal includes performing the first anneal to diffuse elements:

from the second diffusion barrier layer and the metal containing layer into the dielectric layer in the first device region; and

from the diffusion barrier layer into the dielectric layer in the second device region.

4. The method as recited in claim 1, further comprising:

forming a first semiconductor layer over a first cap diffusion barrier layer over the metal containing layer before performing the first anneal; and

removing the first semiconductor layer and the first cap diffusion barrier layer after performing the first anneal.

5. The method as recited in claim 1, further comprising:

forming a second semiconductor layer over a second cap diffusion barrier layer over the dielectric layer before performing the second anneal; and

removing the second semiconductor layer after performing the second anneal.

6. The method as recited in claim 1, wherein the dielectric layer includes a hafnium oxide (HfO2) layer formed over a silicon dioxide (SiO2) layer.

7. The method as recited in claim 6, wherein performing the first anneal includes performing the first anneal to diffuse the elements through the HfO2 layer and at least partially though the SiO2 layer.

8. The method as recited in claim 7, wherein performing the second anneal includes performing the second anneal to regrow at least a portion of the SiO2 layer.

9. The method as recited in claim 1, wherein the metal containing layer includes lanthanum oxide (La2O3) and the diffusion barrier layer includes titanium nitride (TiN).

10. The method as recited in claim 1, further comprising forming at least one workfunction material layer on the dielectric layer.

11. The method as recited in claim 10, further comprising forming a conductive layer over the at least one work function material layer to form a replacement gate stack.

12. A method for semiconductor fabrication, comprising:

forming a dielectric layer in gate cavities associated with first and second device regions;

forming a second diffusion barrier layer over a metal containing layer over the dielectric layer in the first device region, and a first diffusion barrier layer over the dielectric layer in the second device region;

performing a first anneal to diffuse elements from the second diffusion barrier layer and the metal containing layer into the dielectric layer in the first device region, and from the first diffusion barrier into the dielectric layer in the second device region;

removing the second diffusion barrier, the metal containing layer, and the first diffusion barrier; and

performing a second anneal to adjust diffusion of the elements in the dielectric layer to provide a gate dielectric region.

13. The method as recited in claim 12, wherein the dielectric layer includes a hafnium oxide (HfO2) layer formed over a silicon dioxide (SiO2) layer.

14. The method as recited in claim 12, wherein the metal containing layer includes lanthanum oxide (La2O3) and the first and second diffusion barrier layers include titanium nitride (TiN).

15. A semiconductor device, comprising:

a substrate having a plurality of regions including a first region and a second region;

a first gate structure formed in the first region including a first dielectric layer, which has a top layer, middle layer, and bottom layer of the first dielectric layer, the top layer of the first dielectric layer including hafnium (Hf), lanthanum (La), oxygen (O), and nitrogen (N), the middle layer of the first dielectric layer including La, silicon (Si), O, and N, and the bottom layer of the first dielectric layer including undoped silicon dioxide; and

a second gate structure formed in the second region including a second dielectric layer, which has a top layer, middle layer, and bottom layer of the second dielectric layer, the top layer of the second dielectric layer including Hf, O, and N, the middle layer of the second dielectric layer including Si, O, and N, and the bottom layer of the second dielectric layer including undoped silicon dioxide.

16. The semiconductor device as recited in claim 15, wherein the first and second dielectric layers are U-shaped.

17. The semiconductor device as recited in claim 15, wherein vertical portions of the first and second gate dielectric layers contact inner portions of sidewall spacers.

18. The semiconductor device as recited in claim 15, wherein the first gate structure includes a second work function material, and the second gate structure includes a first and the second work function material.

19. The semiconductor device as recited in claim 15, wherein the first and second gate structures include a conductive material.

20. The semiconductor device as recited in claim 15, wherein the first gate structure forms an n-type field effect transistor and the second gate structure forms a p-type field effect transistor.