CLOCK SPURS REDUCTION TECHNIQUE

• US 20150035576A1
• Filed: 10/21/2014
• Published: 02/05/2015
• Est. Priority Date: 07/28/2010
• Status: Active Grant

• Current Assignee: Marvell Asia Pte Limited (Marvell Technology Group Limited)
• Original Assignee: Marvell World Trade Limited (Marvell Technology Group Limited)
• Inventors: ROMANO, Luca
• Granted Patent: US 9,397,647 B2
• Time in Patent Office: Days
• US Class Current: 327/262
• CPC Class Codes: H03K 2005/00058 controlled by a digital setting
• CPC Class Codes: H03K 5/131 Digitally controlled
• CPC Class Codes: H03K 5/133 using a chain of active delay devices
• CPC Class Codes: H03K 5/135 by the use of time reference signals, e.g. clock signals

Abstract

Aspects of the disclosure provide a circuit having a jittered clock generator. The jittered clock generator is configured to add jitter of a controlled characteristic to a first clock signal of a clock frequency to generate a second clock signal to be used by a transceiver for operating at a radio frequency. The jitter of the controlled characteristic adjusts a clock harmonic at the radio frequency of the transceiver.

Claims

1. A circuit comprising:

a jittered clock generator configured to add jitter of a controlled characteristic to a first clock signal of a clock frequency to generate a second clock signal to be used by a transceiver for operating at a radio frequency, the jitter of the controlled characteristic adjusting a clock harmonic at the radio frequency of the transceiver.

2. The circuit of claim 1, wherein the jittered clock generator further comprises:

a jitter controller configured to generate a control signal as a function of the specific clock harmonic; and

a jitter generator configured to add the jitter according to the control signal to the first clock signal to generate the second clock signal.

3. The circuit of claim 2, wherein the jitter generator is configured to add a variable delay to the first clock signal to generate the second clock signal.

4. The circuit of claim 2, wherein the jitter generator comprises a delay chain of a plurality of delay elements to add an additional amount of delay to the first clock signal.

5. The circuit of claim 4, wherein the jitter generator comprises an edge selector configured to vary a selection of one of the delay elements to output the second clock in order to change the variable delay of the second clock signal to the first clock signal.

6. The circuit of claim 5, wherein the jitter controller is configured to generate a sequence of selection codes to control the edge selector to vary the selection of the delay elements.

7. The circuit of claim 6, wherein the jitter controller is configured to generate the sequence of the selection codes to vary the selection of the delay elements in a random manner.

8. The circuit of claim 4, wherein the jitter generator is configured to form a loop that includes the delay chain to calibrate the additional amount of delay added by each delay element to suppress the clock harmonic.

9. The circuit of claim 1, wherein the jittered clock generator is configured to add the jitter of the controlled characteristic to convert a power at the clock harmonic to spurs out of a radio frequency of interest.

10. The circuit of claim 1, wherein the jittered clock generator is configured to add the jitter of the controlled characteristic to convert a power at the clock harmonic to a noise floor.

11. A method comprising:

receiving a first clock signal of a clock frequency; and

adding jitter of a controlled characteristic to the first clock signal to generate a second clock signal to be used by a transceiver for operating at a radio frequency, the jitter of the controlled characteristic adjusting a clock harmonic at the radio frequency of the transceiver.

12. The method of claim 11, wherein adding the jitter of the controlled characteristic to the first clock signal further comprises:

generating a control signal as a function of the clock harmonic; and

adding the jitter according to the control signal to the first clock signal to generate the second clock signal.

13. The method of claim 11, wherein adding the jitter of the controlled characteristic to the first clock signal further comprises:

adding a variable delay to the first clock signal to generate the second clock signal.

14. The method of claim 13, wherein adding the variable delay to the first clock signal further comprises:

delaying the first clock signal via a delay chain of multiple delay elements.

15. The method of claim 14, further comprising:

varying a selection of one of the delay elements to output the second clock.

16. The method of claim 15, further comprising:

generating a sequence of selection codes to control the edge selector to vary the selection of the delay elements.

17. The method of claim 16, further comprising:

generating the sequence of the selection codes to vary the selection of the delay elements in a random manner.

18. The method of claim 14, further comprising:

calibrating the additional amount of delay added by each delay element to suppress the clock harmonic.

19. The method of claim 11, wherein adding the jitter of a controlled characteristic to the first clock signal to generate the second clock signal further comprises:

adding the jitter of the controlled characteristic to convert a power at the clock harmonic to spurs out of a radio frequency band of interest.

20. The method of claim 11, adding the jitter of a controlled characteristic to the first clock signal to generate the second clock signal further comprises:

adding the jitter of the controlled characteristic to convert a power at the clock harmonic to a noise floor.