METHOD FOR FORMING SHIELDED GATE OF MOSFET

• US 20150037968A1
• Filed: 09/06/2013
• Published: 02/05/2015
• Est. Priority Date: 08/05/2013
• Status: Active Grant

• Current Assignee: Mosel Vitelic Incorporated
• Original Assignee: Mosel Vitelic Incorporated
• Inventors: Lai, Richard
• Granted Patent: US 9,006,090 B2
• Time in Patent Office: Days
• US Class Current: 438/589
• CPC Class Codes: H01L 21/28008 Making conductor-insulator-semiconductor electrodes
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A method for forming a shielded gate of a MOSFET includes steps as following: providing a semiconductor substrate having at least one trench, forming a bottom gate oxide region and a shielded gate poly region in the trench of the semiconductor substrate, forming an inter-poly oxide region on the shielded gate poly region through high temperature plasma deposition, poly etching back and oxide etching back; and forming a gate oxide region and a gate poly region on the inter-poly oxide region. By utilizing the etching back processes in replace of traditional chemical mechanical polishing processes, the manufacturing cost of manufacturing a shielded gate structure is reduced, and the total cost of manufacturing a FET is also reduced. Meanwhile, the gate charge is effectively reduced due to the shielded gate structure, so that the performance of a MOSFET is enhanced.

Claims

1. A method for forming a shielded gate of a MOSFET, comprising steps of:

(a) providing a semiconductor substrate having at least one trench;

(b) forming a bottom gate oxide region and a shielded gate poly region in said trench of said semiconductor substrate;

(c) forming an inter-poly oxide region on said shielded gate poly region through high temperature plasma deposition, poly etching back and oxide etching back; and

(d) forming a gate oxide region and a gate poly region on said inter-poly oxide region.

2. The method according to claim 1, wherein said step (a) further comprises steps of:

(a1) providing said semiconductor substrate;

(a2) depositing an oxide layer on said semiconductor substrate;

(a3) patterning a trench photo on said semiconductor substrate and said oxide layer;

(a4) etching said oxide layer;

(a5) photolithographing said trench photo for forming said trench; and

(a6) etching said trench.

3. The method according to claim 2, wherein said oxide layer is a hard mask layer, said step (a4) is implemented through wet etching, and said step (a6) is implemented through dry etching.

4. The method according to claim 1, wherein said step (b) further comprises steps of:

(b1) processing a bottom gate oxide growth on a bottom of said trench for forming said bottom gate oxide region;

(b2) processing a poly-silicon deposition on said bottom gate oxide region for forming said shielded gate poly region; and

(b3) etching back said shielded gate poly region.

5. The method according to claim 1, wherein said step (c) further comprises steps of:

(c1) depositing an oxide through a high temperature plasma oxide deposition;

(c2) depositing a mask poly through a mask poly deposition;

(c3) etching back said mask poly;

(c4) etching back said oxide; and

(c5) removing said mask poly and a portion of said oxide for forming said inter-poly oxide region.

6. The method according to claim 5, wherein a poly stopper is formed through an overhang profile of a high temperature plasma oxide with narrow neck in said step (c1).

7. The method according to claim 5, wherein a void is formed in said trench in said step (c2).

8. The method according to claim 5, wherein said step (c3) and said step (c4) are implemented through etch selectivity.

9. The method according to claim 1, wherein said inter-poly oxide region is formed through self-alignment.

10. The method according to claim 1, wherein said step (d) further comprises steps of:

(d1) processing a gate oxide deposition on said inter-poly oxide region for forming said gate oxide region; and

(d2) processing a gate poly deposition on said inter-poly oxide region and said gate oxide region for forming said gate poly region.