SPEECH RECOGNITION

• US 20150039303A1
• Filed: 06/25/2014
• Published: 02/05/2015
• Est. Priority Date: 06/26/2013
• Status: Active Grant

• Current Assignee: Cirrus Logic Incorporated
• Original Assignee: Wolfson Microelectronics plc
• Inventors: Lesso, John Paul, Hatfield, Robert James
• Granted Patent: US 9,697,831 B2
• Time in Patent Office: Days
• US Class Current: 704/233
• CPC Class Codes: G10L 15/20 Speech recognition techniques specially adapted for robustness in adverse environments, e.g. in noise, of stress induced speech G10L21/02 takes precedence
• CPC Class Codes: G10L 15/28 Constructional details of speech recognition systems
• CPC Class Codes: G10L 17/24 the user being prompted to utter a password or a predefined phrase
• CPC Class Codes: G10L 2015/088 Word spotting
• CPC Class Codes: G10L 21/0208 Noise filtering

Abstract

A speech recognition system comprises: an input, for receiving an input signal from at least one microphone; a first buffer, for storing the input signal; a noise reduction block, for receiving the input signal and generating a noise reduced input signal; a speech recognition engine, for receiving either the input signal output from the first buffer or the noise reduced input signal from the noise reduction block; and a selection circuit for directing either the input signal output from the first buffer or the noise reduced input signal from the noise reduction block to the speech recognition engine.

Claims

1. A speech processing system comprising;

an input for receiving an input signal from at least one microphone,

a first signal path for connecting the input to an output;

a second signal path for connecting the input to the output,

selection circuitry for selecting either the first signal path or the second signal path for carrying the input signal from the input to the output;

wherein

the first signal path contains a first buffer for storing the input signal, and

the second signal path contains a noise reduction block for receiving the input signal and supplying a noise reduced signal to the output, and a second buffer;

wherein

the second buffer imparts a delay in the second signal path such that the noise reduced signal is substantially time-aligned with the output of the first buffer.

2. A speech processing system as claimed in claim 1, further comprising a trigger phrase detection system for determining if the input signal contains a valid trigger phrase spoken by an authorised user,

wherein the trigger phrase detection system is adapted to output a trigger signal to the selection circuitry, and

the selection circuitry is adapted to switch from selecting the first signal path to selecting the second signal path when it receives said trigger signal.

3. A speech processing system as claimed in claim 1, further comprising a trigger phrase detection system for determining if the input signal contains a valid trigger phrase spoken by an authorised user, and

a driver for receiving a gap signal identifying when the input signal represents a gap in speech,

wherein the trigger phrase detection system is adapted to output a tiger signal to the selection circuitry, and

the driver is adapted to output a driver signal to the selection circuitry when it receives the gap signal, wherein

the selection circuitry is adapted to switch from the first signal path to the second signal path after it has received said gap signal and when it receives said driver signal.

4. A speech recognition system as claimed in claim 2, wherein the trigger phrase detection system is adapted to output said trigger signal when it has detected that a valid trigger phrase has been spoken by an authorised user.

5. A speech processing system as claimed in claim 2, wherein the trigger phrase detection system is adapted to output said trigger signal at an intermediary stage of detecting that a valid trigger phrase has been spoken by an authorised user.

6. A speech recognition system as claimed in claim 1, further comprising a trigger phrase detection system which implements a plurality of phases, wherein

the trigger phrase detection system is adapted to send an activation signal to the noise reduction block when it has completed a particular phase, and

the noise reduction block is activated when it receives said activation signal.

7. A speech recognition system as claimed in claim 6, wherein a speech detection phase of the trigger phrase detection system is adapted to detect speech in the input signal, wherein

the trigger phrase detection system is adapted to send the activation signal to the noise reduction block when it has detected speech in the input signal.

8. A speech recognition system as claimed in claim 6, wherein a valid trigger phrase detection phase of the trigger phrase detection system is adapted to detect that a valid trigger phrase has been spoken, wherein

the trigger phrase detection system is adapted to send the activation signal to the noise reduction block when it has detected that a valid trigger phrase has been spoken.

9. A speech recognition system as claimed in claim 6, wherein an authorised trigger phrase detection phase of the trigger phrase detection system is adapted to detect that a valid trigger phrase has been spoken by an authorised user, wherein

the trigger phrase detected system is adapted to send the activation signal to the noise reduction block when it has detected that a valid trigger phrase has been spoken by an authorised user.

10. A speech recognition system as claimed in claim 1, further comprising a signal activity detection block for detecting if the input signal contains speech, wherein

the first buffer comprises,

a first part which is continuously buffering, and

a second part which only starts buffering after the signal activity detection block detects that the input signal contains speech.

11. An integrated circuit comprising a speech recognition system as claimed in claim 1.

12. A communications device comprising an integrated circuit as claimed in claim 11.

13. A method for speech recognition comprising:

receiving an input signal from at least one microphone, and

selecting either a first signal path or a second signal path for carrying the input signal to the output, wherein

the first signal path contains a first buffer for storing the input signal, and

the second signal path contains a noise reduction block for receiving the input signal and supplying a noise reduced signal to the output, and a second buffer;

wherein

the second buffer imparts a delay in the second signal path such that the noise reduced signal is substantially time-aligned with the output of the first buffer.

14. A speech recognition system comprising;

a speech recognition engine,

an input for receiving an input signal from at least one microphone;

a first signal path for connecting the input to the speech recognition engine,

a second signal path for connecting the input to the speech recognition engine, wherein

the second signal path comprises a noise reduction block for receiving the input signal and outputting a noise reduced signal to the speech recognition engine; and

selection circuitry for selecting either the first signal path or the second signal path for carrying the input signal from the input to the speech recognition engine.

15. A speech recognition system as claimed in claim 14, wherein

the speech recognition engine is cloud-based and the input and noise reduction block are contained within a consumer device having a wireless communications capability.

16. A speech recognition system as claimed in claim 14, further comprising a trigger phrase validation system, wherein

the trigger phrase detection system is adapted to output a signal to the speech recognition engine indicating that a valid trigger phrase has been spoken by an authorised user, wherein

the speech recognition engine is enabled when it receives this signal.

17. A speech recognition system as claimed in claim 14, wherein

the speech recognition engine is adapted to send a switch signal to the selection circuitry when there is a gap in speech, and

the selection circuitry switches from the first signal path to the second signal path when it receives said switch signal.

18. A speech processing system as claimed in claim 14, further comprising a trigger phrase detection system for determining if the input signal contains a valid trigger phrase spoken by an authorised user,

wherein the trigger phrase detection system is adapted to output a trigger signal to the selection circuitry, and

the selection circuitry is adapted to switch from selecting the first signal path to selecting the second signal path when it receives said trigger signal.

19. A speech processing system as claimed in claim 14, further comprising a trigger phrase detection system for determining if the input signal contains a valid trigger phrase spoken by an authorised user, and

a driver for receiving a gap signal identifying when the input signal represents a gap in speech,

wherein the trigger phrase detection system is adapted to output a tiger signal to the selection circuitry, and

the driver is adapted to output a driver signal to the selection circuitry when it receives the gap signal, wherein

the selection circuitry is adapted to switch from the first signal path to the second signal path after it has received said gap signal and when it receives said driver signal.

20. A speech recognition system as claimed in claim 18, wherein the trigger phrase detection system is adapted to output said trigger signal when it has detected that a valid trigger phrase has been spoken by an authorised user.

21. A speech processing system as claimed in claim 18, wherein the trigger phrase detection system is adapted to output said trigger signal at an intermediary stage of detecting that a valid trigger phrase has been spoken by an authorised user.

22. A speech recognition system as claimed in claim 14, further comprising a trigger phrase detection system which implements a plurality of phases, wherein

the trigger phrase detection system is adapted to send an activation signal to the noise reduction block when it has completed a particular phase, and

the noise reduction block is activated when it receives said activation signal.

23. A speech recognition system as claimed in claim 22, wherein a speech detection phase of the trigger phrase detection system is adapted to detect speech in the input signal, wherein

the trigger phrase detection system is adapted to send the activation signal to the noise reduction block when it has detected speech in the input signal.

24. A speech recognition system as claimed in claim 22, wherein a valid trigger phrase detection phase of the trigger phrase detection system is adapted to detect that a valid trigger phrase has been spoken, wherein

the trigger phrase detection system is adapted to send the activation signal to the noise reduction block when it has detected that a valid trigger phrase has been spoken.

25. A speech recognition system as claimed in claim 22, wherein an authorised trigger phrase detection phase of the trigger phrase detection system is adapted to detect that a valid trigger phrase has been spoken by an authorised user, wherein

the trigger phrase detected system is adapted to send the activation signal to the noise reduction block when it has detected that a valid trigger phrase has been spoken by an authorised user.

26. A method for speech recognition comprising;

receiving an input signal from at least one microphone, and

selecting either the first signal path or the second signal path, wherein

the second signal path comprises a noise reduction block for receiving the input signal and outputting a noise reduced signal to the speech recognition engine

27. A speech recognition system comprising;

an input for receiving an input signal from at least one microphone

a speech recognition engine, and

noise reduction circuitry for receiving the input signal which produces a noise reduced signal for inputting into the speech recognition engine if a valid trigger phrase spoken by an authorised user is detected in the input signal.

28. A speech recognition system, comprising:

an input, for receiving an input signal from at least one microphone;

a first buffer, for storing the input signal;

a noise reduction block, for receiving the input signal and generating a noise reduced input signal;

a speech recognition engine, for receiving either the input signal output from the first buffer or the noise reduced input signal from the noise reduction block; and

a selection circuit for directing either the input signal output from the first buffer or the noise reduced input signal from the noise reduction block to the speech recognition engine.

29. A speech recognition system as claimed in claim 28, having a pass-phrase validation function for determining from the input signal whether a trigger phrase has been spoken by an authorised user of the system, wherein the selection circuit is controlled to direct the noise reduced input signal from the noise reduction block to the speech recognition engine only after the pass-phrase validation function has determined that the trigger phrase has been spoken by an authorised user of the system.

30. A speech recognition system as claimed in claim 29, wherein:

the selection circuit is controlled to direct the input signal output from the first buffer to the speech recognition engine when the pass-phrase validation function first determines that the trigger phrase has been spoken by an authorised user of the system; and

wherein;

the selection circuit is controlled to direct the noise reduced input signal from the noise reduction block to the speech recognition engine when the speech recognition engine determines that the signal represents a gap in speech.

31. A speech recognition system as claimed in claim 30, comprising a second buffer, for applying a time delay to the noise reduced input signal so that it is substantially in time alignment with the input signal output from the first buffer.

32. An integrated circuit for use in a speech recognition system, comprising:

an input, for receiving an input signal from at least one microphone;

a first buffer, for storing the input signal; and

a noise reduction block comprising a second buffer, for receiving the input signal and generating a buffered noise reduced input signal,

such that either the stored input signal can be output from the first buffer to a speech recognition engine, or the buffered noise reduced input signal can be output from the second buffer to the speech recognition engine.