TRANSMITTER APPARATUS AND SIGNAL PROCESSING METHOD THEREOF

• US 20150039973A1
• Filed: 07/07/2014
• Published: 02/05/2015
• Est. Priority Date: 07/05/2013
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd. (Samsung Group)
• Original Assignee: Samsung Electronics Co. Ltd. (Samsung Group)
• Inventors: JEONG, Hong-sil, MYUNG, Se-ho, KIM, Kyung-joong
• Granted Patent: US 9,484,957 B2
• Time in Patent Office: Days
• US Class Current: 714/776
• CPC Class Codes: H03M 13/11 using multiple parity bits
• CPC Class Codes: H03M 13/1102 Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
• CPC Class Codes: H03M 13/1165 QC-LDPC codes as defined for the digital video broadcasting [DVB] specifications, e.g. DVB-Satellite [DVB-S2]
• CPC Class Codes: H03M 13/1177 Regular LDPC codes with parity-check matrices wherein all rows and columns have the same row weight and column weight, respectively
• CPC Class Codes: H03M 13/255 with Low Density Parity Check [LDPC] codes
• CPC Class Codes: H03M 13/27 using interleaving techniques
• CPC Class Codes: H03M 13/271 Row-column interleaver with permutations, e.g. block interleaving with inter-row, inter-column, intra-row or intra-column permutations
• CPC Class Codes: H03M 13/2778 Interleaver using block-wise interleaving, e.g. the interleaving matrix is sub-divided into sub-matrices and the permutation is performed in blocks of sub-matrices
• CPC Class Codes: H03M 13/2792 Interleaver wherein interleaving is performed jointly with another technique such as puncturing, multiplexing or routing
• CPC Class Codes: H03M 13/356 Unequal error protection [UEP]
• CPC Class Codes: H03M 13/616 Matrix operations, especially for generator matrices or check matrices, e.g. column or row permutations
• CPC Class Codes: H03M 13/6538 ATSC VBS systems
• CPC Class Codes: H03M 13/6552 DVB-T2
• CPC Class Codes: H03M 13/6555 DVB-C2
• CPC Class Codes: H04L 1/00 Arrangements for detecting or preventing errors in the information received correcting synchronisation H04L7/00
• CPC Class Codes: H04L 1/004 by using forward error control H04L1/0618 takes precedence; coding, decoding or code conversion, for error detection or correction H03M13/00
• CPC Class Codes: H04L 1/0041 Arrangements at the transmitter end
• CPC Class Codes: H04L 1/0057 Block codes H04L1/0061, H04L1/0064 take precedence
• CPC Class Codes: H04L 1/0071 Use of interleaving interleaving per se H03M13/27
• CPC Class Codes: H04L 27/04 Modulator circuits; Transmitter circuits
• CPC Class Codes: H04L 27/36 : Modulator circuits; Transmitter circuits

Abstract

A transmitter apparatus and a receiver apparatus are provided. The transmitter apparatus includes: an encoder configured to generate a low density parity check (LDPC) by performing LDPC encoding; an interleaver configured to interleave the LDPC codeword; and a modulator configured to map the interleaved LDPC codeword onto a modulation symbol. The modulator maps a bit included in a predetermined group from among a plurality of groups constituting the LDPC codeword onto a predetermined bit in the modulation symbol.

Claims

1. A transmitter apparatus comprising:

an encoder configured to generate a low density parity check (LDPC) codeword by performing LDPC encoding;

an interleaver configured to interleave the LDPC codeword; and

a modulator configured to map the interleaved LDPC codeword onto a modulation symbol,

wherein the modulator is configured to map a bit included in a predetermined group from among a plurality of groups constituting the LDPC codeword onto a predetermined bit in the modulation symbol.

2. The transmitter apparatus of claim 1, wherein each of the plurality of groups is formed of 360 bits.

3. The transmitter apparatus of claim 1, wherein the interleaver comprises:

a parity interleaver configured to interleave parity bits constituting the LDPC codeword;

a group interleaver configured to perform group-interleaving by dividing the parity-interleaved LDPC codeword into the plurality of groups and rearranging an order of the plurality of groups in; and

a block interleaver configured to perform block-interleaving of the plurality of groups the order of which has been rearranged.

4. The transmitter apparatus of claim 3, wherein the group interleaver rearranges the order of the plurality of groups based on a following equation:

Y_j=X<sub>π

(j)</sub>(0≦

j<

N_group)

where X_j is a j^th group before the group-interleaving, Y_j is a j^th group after the group-interleaving, N_group is a total number of the plurality of groups, and π

(j) is a parameter indicating an interleaving order.

5. The transmitter apparatus of claim 4, wherein π

(j) is determined based on at least one of a length of the LDPC codeword, a modulation method and a code rate.

6. The transmitter apparatus of claim 5, wherein π

(j) is defined as in a following table when the length of the LDPC codeword is 64800, the modulation method is 256-QAM, and the code rate is 6/15;

7. The transmitter apparatus of claim 5, wherein π

(j) is defined as in a following table when the length of the LDPC codeword is 64800, the modulation method is 256-QAM, and the code rate is 8/15;

8. The transmitter apparatus of claim 5, wherein π

(j) is defined as in a following table when the length of the LDPC codeword is 64800, the modulation method is 256-QAM, and the code rate is 10/15;

9. The transmitter apparatus of claim 5, wherein π

(j) is defined as in a following table when the length of the LDPC codeword is 64800, the modulation method is 256-QAM, and the code rate is 10/15;

10. The transmitter apparatus of claim 5, wherein π

(j) is defined as in a following table when the length of the LDPC codeword is 64800, the modulation method is 256-QAM, and the code rate is 12/15;

11. The transmitter apparatus of claim 3, wherein the block interleaver is configured to perform the block-interleaving by writing the plurality of groups in each of a plurality of columns in group units in a column direction, and reading each row of the plurality of columns in which the plurality of groups are written in group units in a row direction.

12. The transmitter apparatus of claim 11, wherein, for the writing the plurality of groups in each of the plurality of columns, the block interleaver is configured to divide the plurality of columns in at least two parts, write at least some groups among the plurality of groups in a first part of each of the plurality of columns serially, and write the remaining of the plurality of groups in the other part of each of the plurality of columns.

13. The transmitter apparatus of claim 11, wherein the group interleaver is configured to rearrange the order of the plurality of groups such that groups comprising a bit to be mapped onto a same location of different modulation symbols are serially arranged to be adjacent to one another so that the block interleaver writes a predetermined group among the plurality of groups in a predetermined column among the plurality of columns.

14. The transmitter apparatus of claim 13, wherein the modulator is configured to generate the modulation symbol by mapping a bit output from the predetermined column onto a predetermined bit in the modulation symbol.

15. A signal processing method of a transmitter apparatus, the signal processing method comprising:

generating a low density parity check (LDPC) codeword by performing LDPC encoding;

interleaving the LDPC codeword; and

mapping the interleaved LDPC codeword onto a modulation symbol,

wherein the mapping the interleaved LDPC codeword onto the modulation symbol comprises mapping a bit included in a predetermined group from among a plurality of groups constituting the LDPC codeword onto a predetermined bit in the modulation symbol.

16. The signal processing method of claim 15, wherein each of the plurality of groups is formed of 360 bits.

17. The signal processing method of claim 15, wherein the interleaving comprises:

interleaving parity bits constituting the LDPC codeword;

group-interleaving by dividing the parity-interleaved LDPC codeword into the plurality of groups and rearranging an order of the plurality of groups; and

block-interleaving the plurality of groups the order of which has been rearranged.

18. The signal processing method of claim 17, wherein the rearranging the order of the plurality of groups in the group-wise fashion comprises rearranging the order of the plurality of groups in the group-wise fashion based on a following equation:

Y_j=X<sub>π

(j)</sub>(0≦

j<

N_group)

where X_j is a j^th group before the group-interleaving, Y_j is a j^th group after the group-interleaving, N_group is a total number of the plurality of groups, and π

(j) is a parameter indicating an interleaving order.

19. The signal processing method of claim 18, wherein π

(j) is determined based on at least one of a length of the LDPC codeword, a modulation method, and a code rate.

20. The signal processing method of claim 19, wherein π

(j) is defined as in a following table when the length of the LDPC codeword is 64800, the modulation method is 256-QAM, and the code rate is 6/15;

21. The signal processing method of claim 19, wherein π

(j) is defined as in a following table when the length of the LDPC codeword is 64800, the modulation method is 256-QAM, and the code rate is 8/15;

22. The signal processing method of claim 19, wherein π

(j) is defined as in a following table when the length of the LDPC codeword is 64800, the modulation method is 256-QAM, and the code rate is 10/15;

23. The signal processing method of claim 19, wherein π

(j) is defined as in a following table when the length of the LDPC codeword is 64800, the modulation method is 256-QAM, and the code rate is 10/15;

24. The signal processing method of claim 19, wherein π

(j) is defined as in a following table when the length of the LDPC codeword is 64800, the modulation method is 256-QAM, and the code rate is 12/15;

25. The signal processing method of claim 17, wherein the block-interleaving the plurality of groups comprises:

performing the block-interleaving by writing the plurality of groups in each of a plurality of columns in group units in a column direction; and

reading each row of the plurality of columns in which the plurality of groups are written in group units in a row direction.

26. The signal processing method of claim 25, wherein the block-interleaving the plurality of groups comprises:

dividing the plurality of columns in at least two parts;

writing at least some groups among the plurality of groups in a first part of each of the plurality of columns serially; and

writing the remaining of the plurality of groups in the other part of each of the plurality of columns.

27. The signal processing method of claim 25, wherein the rearranging the order of the plurality of groups is performed such that groups comprising a bit to be mapped onto a same location of different modulation symbols are serially arranged to be adjacent to one another so that a predetermined group among the plurality of groups is written on a predetermined column among the plurality of columns.

28. The signal processing method of claim 27, wherein the mapping the LDPC codeword onto the modulation symbol comprises generating the modulation symbol by mapping a bit output from the predetermined column onto a predetermined bit in the modulation symbol.