MULTI-PATTERNING MASK DECOMPOSITION METHOD AND SYSTEM

• US 20150040077A1
• Filed: 07/31/2013
• Published: 02/05/2015
• Est. Priority Date: 07/31/2013
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: HO, Chia-Ming, SU, Ke-Ying, LEE, Hsien-Hsin Sean, TSAI, Kun-Ting, WU, Tsung-Han
• Granted Patent: US 8,954,900 B1
• Time in Patent Office: Days
• US Class Current: 716/51
• CPC Class Codes: G03F 7/70433 Layout for increasing efficiency or for compensating imaging errors, e.g. layout of exposure fields for reducing focus errors; Use of mask features for increasing efficiency or for compensating imaging errors
• CPC Class Codes: G03F 7/70466 Multiple exposures, e.g. combination of fine and coarse exposures, double patterning or multiple exposures for printing a single feature stitching G03F7/70475

Abstract

A portion of a layout of a single layer of an integrated circuit is to be multi-patterned. The patterns are divided into first and second groups, to be patterned on the single layer by a first mask or a second mask. For each portion of each pattern, a spacing relationship is determined between that portion and any adjacent pattern on either or both sides. A processor computes a first capacitance (C), resistance (R), or resistance-capacitance (RC) cost of assigning the first group to the first mask and the second group to the second mask, and a second cost of assigning the first group to the second mask and the second group to the first mask, based on the spacing relationships. The first group is assigned to the first mask and the second group to the second mask if the first cost is lower than the second cost.

Claims

1. A method, comprising:

providing a portion of a layout of a single layer of an integrated circuit to be multi-patterned, the portion of the layout having a plurality of patterns representing circuit elements, the patterns including lines and divided into at least a first group and a second group, each of the first and second groups to be patterned on the single layer by a respectively different one of a first mask in a first process or a second mask in a second process, wherein a line width bias of the second process is different from a line width bias of the first process;

for each respective portion of each one of the plurality of patterns, determining a spacing relationship between that portion of that pattern and any adjacent pattern on either or both sides of that pattern;

computing, in a processor, a first capacitance (C), resistance (R), or resistance-capacitance (RC) cost of assigning the first group to the first mask and the second group to the second mask, and a second C, R or RC cost of assigning the first group to the second mask and the second group to the first mask, the computing based on the spacing relationships; and

assigning, by the processor, the first group to the first mask and the second group to the second mask if the first C, R or RC cost is lower than the second C, R or RC cost, and

assigning, by the processor, the first group to the second mask and the second group to the first mask if the first C, R or RC cost is higher than the second C, R or RC cost.

2. The method of claim 1, further comprising assigning, by the processor, the first group to the second mask and the second group to the first mask if the second C, R or RC cost is lower than the first C, R or RC cost.

3. The method of claim 1, wherein the step of determining a spacing relationship comprises classifying each portion of each pattern as either having either dense spacing on both sides, dense spacing on one side and isolated spacing on the other side, or isolated spacing on both sides.

4. The method of claim 3, wherein the computing step includes assigning a weight to each spacing relationship, and multiplying the length of each respective portion of each pattern by the weight assigned to the spacing relationship of that portion of that pattern.

6. The method of claim 1, wherein the patterns of the layout are lines, to be patterned in the layer using a process for which a line width of a line formed by the second mask depends on a distance between that line and a nearest adjacent line on each side of that line.

7. The method of claim 1, wherein the second mask is to be formed by spacers in the layer of the substrate, the spacers to be formed on side walls of lines to be patterned by the first mask.

8. The method of claim 1, further comprising:

generating a conflict graph representing the layout, the conflict graph having a respective vertex corresponding to each respective pattern and an edge connecting each pair of vertices corresponding to a respective pair of patterns separated from each other by a spacing smaller than a threshold distance;

partitioning the graph into a plurality of sub-graphs, such that each vertex in each sub-graph is connected to at least one other vertex in the same sub-graph, and is unconnected to any vertex in any other sub-graph, one of the sub-graphs corresponding to the plurality of patterns.

9. The method of claim 8, further comprising:

identifying at least one isolated vertex having no edge connection to another vertex in any of the plurality of sub-graphs, the isolated vertex representing a pattern having isolated spacing on both sides;

selecting a criterion from the group consisting of capacitance or resistance;

evaluating respective costs, based on the selected criterion, of including the pattern corresponding to the isolated vertex in the first mask and of including the pattern in the second mask; and

assigning the pattern corresponding to the isolated vertex to the one of the first mask or second mask corresponding to the lower evaluated cost.

10. The method of claim 9, wherein:

the patterns of the layout are lines, to be patterned in the layer using a process for which the second mask has a different line width bias than the first mask;

the pattern corresponding to the isolated vertex is assigned to the first mask if the selected criterion is capacitance; and

the pattern corresponding to the isolated vertex is assigned to the second mask if the selected criterion is resistance.

21. The method of claim 3, wherein the computing includes assigning a cost of zero for each pattern having dense spacing on both sides that is assigned to the second mask.

22. The method of claim 4, wherein a weight assigned to a pattern having isolated spacing on both sides is greater than a weight assigned to a pattern having dense spacing on one side thereof and isolated spacing on an opposite side thereof.

5. (canceled)

11. A routing method, comprising:

providing a portion of a layout of a single layer of an integrated circuit to be multi-patterned, the portion of the layout having a plurality of patterns representing circuit elements, the patterns including lines and divided into at least a first group and a second group, first group to be patterned on the single layer by a first mask in a first process, the second group to be patterned on the single layer by a second mask in a second process, wherein a line width bias of the second process is different from a line width bias of the first process;

identifying an additional pattern of the layout separated from a nearest neighboring one of the plurality of patterns by at least a threshold distance;

computing, in a processor, a first resistance (R) or resistance-capacitance (RC) cost of assigning the additional pattern to the first mask, and a second R or RC cost of assigning the additional pattern to the second mask, the computing based on a respective spacing relationship between each respective portion of the additional pattern and any adjacent pattern within the plurality of patterns on either or both sides of that portion;

assigning the additional pattern to the first mask if the first R or RC cost is lower than the second R or RC cost, and

assigning the additional pattern to the second mask if the second R or RC cost is lower than the first R or RC cost.

12. The method of claim 11, further comprising:

computing, in the processor, a first capacitance (C), R, or RC cost of assigning the first group to the first mask and the second group to the second mask, and a second C, R or RC cost of assigning the first group to the second mask and the second group to the first mask, the computing based on a respective spacing relationship between each respective portion of each pattern and any adjacent pattern on either or both sides of that portion; and

assigning, by the processor, the first group to the first mask and the second group to the second mask if the first C, R or RC cost is lower than the second C, R or RC cost.

13. The method of claim 12, further comprising assigning, by the processor, the first group to the second mask and the second group to the first mask if the second C, R or RC cost is lower than the first C, R or RC cost.

14. The method of claim 11, wherein the spacing relationship is determined by classifying each portion of each pattern as either having either dense spacing on both sides, dense spacing on one side and isolated spacing on the other side, or isolated spacing on both sides.

15. The method of claim 11, wherein the computing step includes assigning a weight to each spacing relationship, and multiplying the length of each respective portion of each pattern by the weight assigned to the spacing relationship of that portion of that pattern.

16. (canceled)

17. A system, comprising:

a non-transitory, machine readable storage medium encoded with data representing a portion of a layout of a single layer of an integrated circuit to be multi-patterned, the portion of the layout having a plurality of patterns representing circuit elements, the patterns including lines and divided into at least a first group and a second group, each of the first and second groups to be patterned on the single layer by a respectively different one of a first mask in a first process or a second mask in a second process, wherein a line width bias of the second process is different from a line width bias of the first process; and

a processor coupled to access the storage medium, the processor programmed to perform a method comprising;

for each respective portion of each one of the plurality of patterns, determining a spacing relationship between that portion of that pattern and any adjacent pattern on either or both sides of that pattern;

computing, in a processor, a first capacitance (C), resistance (R), or resistance-capacitance (RC) cost of assigning the first group to the first mask and the second group to the second mask, and a second C, R or RC cost of assigning the first group to the second mask and the second group to the first mask, the computing based on the spacing relationships;

assigning, by the processor, the first group to the first mask and the second group to the second mask if the first C, R or RC cost is lower than the second C, R or RC cost, and

assigning, by the processor, the first group to the second mask and the second group to the first mask if the first C, R or RC cost is higher than the second C, R or RC cost.

18. The system of claim 17, wherein the method further comprises assigning, by the processor, the first group to the second mask and the second group to the first mask if the second C, R or RC cost is lower than the first C, R or RC cost.

19. The system of claim 17, wherein the step of determining a spacing relationship comprises classifying each portion of each pattern as either having either dense spacing on both sides, dense spacing on one side and isolated spacing on the other side, or isolated spacing on both sides.

23. The system of claim 19, wherein the computing includes assigning a cost of zero for each pattern having dense spacing on both sides that is assigned to the second mask, and a weight assigned to a pattern having isolated spacing on both sides is greater than a weight assigned to a pattern having dense spacing on one side thereof and isolated spacing on an opposite side thereof.

20. (canceled)