Nonvolatile Memory Bitcell With Inlaid High K Metal Select Gate

• US 20150041875A1
• Filed: 08/08/2013
• Published: 02/12/2015
• Est. Priority Date: 08/08/2013
• Status: Active Grant

• Current Assignee: NXP USA, Inc. (NXP Semiconductors NV)
• Original Assignee: Freescale Semiconductor, Inc. (NXP Semiconductors NV)
• Inventors: Perera, Asanga H.
• Granted Patent: US 9,082,837 B2
• Time in Patent Office: Days
• US Class Current: 257/314
• CPC Class Codes: H01L 29/40114 the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
• CPC Class Codes: H01L 29/42328 with at least one additional gate other than the floating gate and the control gate, e.g. program gate, erase gate or select gate
• CPC Class Codes: H01L 29/66477 with an insulated gate, i.e. MISFET
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/66825 with a floating gate H01L29/6684 takes precedence
• CPC Class Codes: H01L 29/78 with field effect produced by an insulated gate H01L29/7725, H01L29/775, H01L29/778 take precedence
• CPC Class Codes: H01L 29/7881 Programmable transistors with only two possible levels of programmation H01L29/7888 takes precedence
• CPC Class Codes: H10B 41/30 characterised by the memory core region
• CPC Class Codes: H10B 41/42 Simultaneous manufacture of periphery and memory cells

Abstract

A process integration is disclosed for fabricating non-volatile memory (NVM) cells having recessed control gates (118, 128) on a first substrate area (111) which are encapsulated in one or more planar dielectric layers (130) prior to forming in-laid high-k metal select gates and CMOS transistor gates (136, 138) in first and second substrate areas (111, 113) using a gate-last HKMG CMOS process flow without interfering with the operation or reliability of the NVM cells.

Claims

1. A semiconductor fabrication process comprising:

forming a plurality of split-gate structures over one or more first substrate areas of a wafer, each split-gate structure comprising a sacrificial poly select gate, a nanocrystal stack, and a recessed control gate formed adjacent to the nanocrystal stack with an upper surface which is recessed below an upper surface of the sacrificial poly select gate;

forming a plurality of sacrificial transistor gate structures over one or more second substrate areas of the wafer, each sacrificial transistor gate structure comprising a sacrificial poly gate having an upper surface with is substantially coplanar with the upper surface of the sacrificial poly select gate;

forming a planarized dielectric layer over the wafer which protects at least the recessed control gate in each split-gate structure and which exposes at least the upper surface of the sacrificial poly select gate and each sacrificial poly gate;

selectively removing at least the sacrificial poly select gates and the sacrificial poly gates to form a plurality of gate electrode openings in the planarized dielectric layer without removing any recessed control gate; and

forming a plurality of high-k metal gate electrodes in the plurality of gate electrode openings while protecting each recessed control gate in each split-gate structure with the planarized dielectric layer, thereby forming high-k metal select gates to replace the sacrificial poly select gates in the plurality of split-gate structures.

2. The semiconductor fabrication process of claim 1, where forming the plurality of split-gate structures comprises forming a plurality of split-gate storage bitcells, each comprising a recessed polysilicon control gate formed adjacent to the nanocrystal stack by depositing a barrier metal layer and a polysilicon layer over the sacrificial poly select gate and nanocrystal stack, and then polishing the polysilicon layer and barrier metal layer to form a polished polysilicon layer which is etched to form a recessed polysilicon control gate having an upper surface which is recessed below the upper surface of the sacrificial poly select gate.

3. The semiconductor fabrication process of claim 1, where forming the planarized dielectric layer comprises:

depositing a dielectric layer over the wafer to cover the plurality of split-gate structures and the plurality of sacrificial transistor gate structures, and

planarizing the dielectric layer with a chemical mechanical polish process to form a substantially flat upper surface to protect at least the recessed control gate in each split-gate structure and to expose at least the upper surface of the sacrificial poly select gate and each sacrificial poly gate.

4. The semiconductor fabrication process of claim 1 where forming the plurality of high-k metal gate electrodes comprises:

forming a metal layer in the plurality of gate electrode openings; and

polishing the metal layer down to be substantially coplanar with the planarized dielectric layer to define the plurality of high-k metal gate electrodes, each having an upper surface which is elevated above the upper surface of the recessed control gate.

5. The semiconductor fabrication process of claim 1, where forming the plurality of high-k metal gate electrodes comprises:

forming a plurality of in-laid metal select gates in the plurality of gate electrode openings to cover at least a high-k gate dielectric layer, each in-laid metal select gate replacing a corresponding sacrificial poly select gate while protecting a corresponding recessed control gate with the planarized dielectric layer.

6. The semiconductor fabrication process of claim 1, where forming the plurality of high-k metal gate electrodes comprises:

forming a plurality of metal transistor gates in the plurality of gate electrode openings to cover at least a high-k gate dielectric layer, each metal transistor gate replacing a corresponding sacrificial poly gate.

7. The semiconductor fabrication process of claim 1, where selectively removing at least the sacrificial poly select gates and sacrificial poly gates comprises:

applying one or more poly etch processes to remove the sacrificial poly select gates and sacrificial poly gates from the plurality of split-gate structures and the plurality of sacrificial transistor gate structures without removing any recessed control gate.

8. The semiconductor fabrication process of claim 1, where forming the plurality of sacrificial transistor gate structures comprises:

forming one or more high-k dielectric layers over the one or more second substrate areas of the wafer using a dielectric material which has a dielectric constant value of 7.0 or greater;

depositing one or more barrier metal layers over the one or more high-k dielectric layers;

depositing one or more polysilicon gate electrode layers over the one or more barrier metal layers; and

patterning and etching the one or more polysilicon gate electrode layers, barrier metal layers, and high-k dielectric layers formed over the one or more second substrate areas to form the plurality of sacrificial transistor gate structures while protecting the recessed control gate in each split-gate structure.

9. The semiconductor fabrication process of claim 8, where selectively removing at least the sacrificial poly select gates and sacrificial poly gates comprises applying one or more poly etch processes to remove the one or more polysilicon gate electrode layers to expose an underlying barrier metal layer in the plurality of gate electrode openings.

10. The semiconductor fabrication process of claim 9, where forming the plurality of high-k metal gate electrodes comprises:

depositing a first metal interface layer in the plurality of gate electrode openings to cover an underlying barrier metal layer;

depositing one or more metal gate electrode layers in the plurality of gate electrode openings to cover the first metal interface layer; and

applying one or more polish and/or etch steps to form a plurality of planarized high-k metal-gate electrodes that are substantially coplanar with the planarized dielectric layer.

11. A method for forming a semiconductor device comprising:

providing a wafer comprising a logic region and a non-volatile memory region;

forming a sacrificial select gate electrode over the non-volatile memory region and a protective stack over the logic region;

forming a non-volatile memory cell structure over the non-volatile memory region, where the non-volatile memory cell structure comprises;

a recessed control gate electrode with an upper surface that is below an upper surface of the sacrificial select gate electrode; and

one or more source/drain regions in the non-volatile memory region of the wafer that are adjacent to the sacrificial select gate electrode;

patterning and etching the protective stack to form a sacrificial transistor gate structure over the logic region;

forming a plurality of metal gates by replacing the sacrificial select gate electrode with a metal select gate electrode in the non-volatile memory region while replacing the sacrificial transistor gate structure with a metal gate electrode in the logic region using a replacement gate process.

12. The method of claim 11, where forming the sacrificial select gate electrode and protective stack comprises:

forming a first dielectric layer on the wafer over the logic region and non-volatile memory region;

forming a first polysilicon layer on the first dielectric layer over the logic region and non-volatile memory region;

forming a second dielectric layer on the first polysilicon layer over the logic region and non-volatile memory region; and

patterning the second dielectric layer, first polysilicon layer, and first dielectric layer to define one or more dielectric-capped sacrificial select gate electrodes over the non-volatile memory region and to define a dielectric-capped protective stack over the logic region.

13. The method of claim 11, where forming the sacrificial select gate electrode and protective stack comprises:

forming the sacrificial select gate electrode in the non-volatile memory region with a patterned poly select gate formed over a high-k gate dielectric layer and barrier metal layer; and

forming the protective stack in the logic region with a patterned poly protective layer formed over a high-k gate dielectric layer and barrier metal layer.

14. The method of claim 11, where forming the non-volatile memory cell structure comprises forming a split-gate thin film storage bitcell comprising a recessed polysilicon control gate electrode formed by polishing and etching a polysilicon layer formed over a nanocrystal layer so that the recessed polysilicon control gate electrode has an upper surface that is below an upper surface of the sacrificial select gate electrode.

15. The method of claim 11, where forming the non-volatile memory cell structure comprises:

depositing a polysilicon layer to cover a charge storage layer formed on the sacrificial select gate electrode in the non-volatile memory region;

applying a chemical mechanical polish to planarize the polysilicon layer into a polished polysilicon layer having an upper surface that is substantially coplanar with the upper surface of the sacrificial select gate electrode; and

applying a recess etch to the polished polysilicon layer to form a recessed polysilicon layer to be adjacent to a portion of the charge storage layer which separates the recessed polysilicon layer from the sacrificial select gate electrode.

16. The method of claim 15, further comprising patterning and etching the recessed polysilicon layer and part of the charge storage layer formed over the sacrificial select gate electrode to form the non-volatile memory cell structure.

17. The method of claim 11, where patterning and etching the protective stack comprises applying one or more etch processes to the protective stack using a patterned etch mask.

18. The method of claim 11, where forming the non-volatile memory cell structure comprises:

depositing barrier metal layer to cover the charge storage layer on a top and sidewall surface of the sacrificial select gate electrode in the non-volatile memory region;

forming a polysilicon layer on the barrier metal layer;

applying a first chemical mechanical polish to planarize the polysilicon layer down to the barrier metal layer formed on top of the sacrificial select gate electrode; and

applying a second chemical mechanical polish to remove the barrier metal layer from the top of the sacrificial select gate electrode, thereby forming a polished polysilicon layer adjacent to the sacrificial select gate electrode which has an upper surface that is substantially coplanar with the top of the sacrificial select gate electrode; and

applying a recess etch to the polished polysilicon layer to form the recessed control gate electrode as a recessed polysilicon layer which has an upper surface that is recessed below the upper surface of the sacrificial select gate electrode.

19. The method of claim 11, where forming the plurality of metal gates comprises:

forming one or more sacrificial transistor gate electrodes over the logic region of the wafer while protecting the recessed control gate electrode of the non-volatile memory cell structure with one or more protective dielectric layers;

forming a planarized dielectric layer which exposes an upper surface of the one or more sacrificial transistor gate electrodes and the upper surface of the sacrificial select gate electrode;

selectively removing at least part of the one or more sacrificial transistor gate electrodes and the sacrificial select gate electrode to form gate electrode openings in the planarized dielectric layer; and

forming a high-k metal gate electrode in each gate electrode opening.

20. A semiconductor device with integrated logic and non volatile memory cells, comprising:

a semiconductor substrate comprising a logic region and a non-volatile memory region;

one or more split-gate thin film storage bitcells formed in the non-volatile memory region of the semiconductor substrate, each comprising a high-k metal select gate electrode, a nanocrystal stack layer located on a sidewall of the high-k metal select gate electrode, and a polished control gate having an upper surface which is recessed below an upper surface of the high-k metal select gate electrode; and

one or more high-k metal gate logic transistors formed in the logic region of the semiconductor substrate, where the one or more high-k metal gate logic transistors comprise gate electrodes that are substantially coplanar with the high-k metal select gate electrode.