Addressable test circuit and test method for key parameters of transistors
First Claim
1. A test method for testing a plurality of transistors, the method comprising:
- measuring a saturation current and a leakage current of a transistor respectively through different test signal lines.
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Abstract
Methods of testing key parameters of transistors can be achieved using an addressable test circuit. Saturation current and leakage current of transistor are measured through different test signal lines. The addressable test circuit can be applied to a plurality of MOS transistors, each MOS transistor has a gate end G, a drain end D, a source end S, and a substrate B, wherein the S end and D end of each MOS transistor are respectively connected to different test signal lines. The test circuit can have a high area utilization rate such that it has the capacity to put a lot of transistors within one small wafer area. In addition, each transistor'"'"'s Idsat, Ioff can be measured accurately.
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Citations
10 Claims
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1. A test method for testing a plurality of transistors, the method comprising:
- measuring a saturation current and a leakage current of a transistor respectively through different test signal lines.
- 2. An addressable test circuit configured to measure key parameters of a transistor, said addressable test circuit applicable to a plurality of MOS transistors, each MOS transistor having a gate end G, a drain end D, a source end S, and a substrate B, where the S end and the D end of each MOS transistor are respectively connected to different test signal lines.
Specification