Addressable test circuit and test method for key parameters of transistors

• US 20150042372A1
• Filed: 10/26/2014
• Published: 02/12/2015
• Est. Priority Date: 11/28/2012
• Status: Abandoned Application

• Current Assignee: Semitronix Corporation
• Original Assignee: Semitronix Corporation
• Inventors: ZHENG, YONGJUN, PAN, WEIWEI
• Application Number:
  US14/523,927
• Publication Number:
  US 20150042372A1
• Time in Patent Office: Days
• US Class Current: 324/762.01
• CPC Class Codes: G01R 31/2601 Apparatus or methods therefor G01R31/2607, G01R31/2642 take precedence
• CPC Class Codes: G01R 31/2607 Circuits therefor G01R31/2642 takes precedence
• CPC Class Codes: G01R 31/2621 for testing field effect transistors, i.e. FET's
• CPC Class Codes: G11C 2029/5002 Characteristic
• CPC Class Codes: G11C 2029/5006 Current
• CPC Class Codes: G11C 29/50008 of impedance
• CPC Class Codes: H01L 22/34 Circuits for electrically characterising or monitoring manufacturing processes, e. g. whole test die, wafers filled with test structures, on-board-devices incorporated on each die, process control monitors or pad structures thereof, devices in scribe line switching, multiplexing, gating devices G01R19/25; process control with lithography, e.g. dose control, G03F7/20; structures for alignment control by optical means G03F7/70633
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

Methods of testing key parameters of transistors can be achieved using an addressable test circuit. Saturation current and leakage current of transistor are measured through different test signal lines. The addressable test circuit can be applied to a plurality of MOS transistors, each MOS transistor has a gate end G, a drain end D, a source end S, and a substrate B, wherein the S end and D end of each MOS transistor are respectively connected to different test signal lines. The test circuit can have a high area utilization rate such that it has the capacity to put a lot of transistors within one small wafer area. In addition, each transistor'"'"'s I_dsat, I_off can be measured accurately.

Claims

1. A test method for testing a plurality of transistors, the method comprising:

measuring a saturation current and a leakage current of a transistor respectively through different test signal lines.

2. An addressable test circuit configured to measure key parameters of a transistor, said addressable test circuit applicable to a plurality of MOS transistors, each MOS transistor having a gate end G, a drain end D, a source end S, and a substrate B, where the S end and the D end of each MOS transistor are respectively connected to different test signal lines.

3. The addressable test circuit of claim 2, wherein one of the S end or the D end of each MOS transistor is connected to a first test signal line, and is also connected to a second signal line through a switch;

another one of the S end or the D end of each MOS transistor is connected to a third test signal line and a fourth signal line through another switch;

wherein, a state of all switches are controlled through selection signals generated by an addressable circuit comprising combinational logic circuits.

4. The addressable test circuit of claim 3, wherein the S end of each MOS transistor is connected to a test signal line SF, and via a switch S_SS connected another test signal line SS;

the D end of each MOS transistor, through switches S_DF, S_DL, is connected to test signal lines DF, DL, respectively.

5. The addressable test circuit of claim 4, wherein the switch S_DF, S_DL, S_SS are transmission gates or individual MOS transistors.

6. The addressable test circuit of claim 5, wherein the switch S_DL comprises an NMOS, and wherein the switches S_DF, S_SS are transmission gates.

7. The addressable test circuit of claim 4, wherein the S end of each MOS transistor is connected to the test signal line SF through the switch S_SF.

8. A test method of the addressable test circuit according to claim 4, comprising:

selecting one of the MOS transistors as a DUT through the addressable circuit;

closing the switches S_DF, S_DL, S_SS connected to the selected MOS transistor;

opening all switches connected to the unselected MOS transistors, and measuring a saturation current I_dsat in a DF terminal.

9. The test method of claim 8, wherein the D end and the S end of the selected MOS transistor form an applied or an induced voltage coupling, the method comprising:

while applying the voltage, measuring a voltage of the D end or the S end through the induced voltage, determining whether the measured voltage meets measurement conditions and accordingly adjusting the applied voltage.

10. A test method with the addressable test circuit of claim 4, comprising:

selecting one of the MOS transistor as a DUT through the addressable circuit, closing the switch S_DL connected to the selected MOS transistor and the switches S_DF, S_SS connected to the unselected MOS transistors, while opening all other switches, equalizing a source voltage at DF and DL terminals, and measuring a subthreshold leakage current I_off at a DL terminal.