SYSTEMS AND METHODS FOR INTEGRATED VOLTAGE REGULATORS

• US 20150042400A1
• Filed: 07/16/2014
• Published: 02/12/2015
• Est. Priority Date: 01/18/2012
• Status: Abandoned Application

• Current Assignee: Trustees Of Columbia University In The City Of New York (Columbia University)
• Original Assignee: Trustees Of Columbia University In The City Of New York (Columbia University)
• Inventors: Sturcken, Noah Andrew, Shepard, Kenneth L.
• Application Number:
  US14/333,427
• Publication Number:
  US 20150042400A1
• Time in Patent Office: Days
• US Class Current: 327/540
• CPC Class Codes: G05F 1/465 Internal voltage generators for integrated circuits, e.g. step down generators
• CPC Class Codes: H01F 17/0006 Printed inductances printed coils for dynamo-electric machines H02K3/26; printed circuits H05K
• CPC Class Codes: H01F 2017/0066 with a magnetic layer
• CPC Class Codes: H01F 41/046 structurally combined with ferromagnetic material
• CPC Class Codes: H01L 21/76879 by selective deposition of conductive material in the vias, e.g. selective C.V.D. on semiconductor material, plating plating on semiconductors in general H01L21/288
• CPC Class Codes: H01L 21/76898 formed through a semiconductor substrate
• CPC Class Codes: H01L 2224/49171 Fan-out arrangements
• CPC Class Codes: H01L 2225/06506 Wire or wire-like electrical connections between devices
• CPC Class Codes: H01L 2225/0651 Wire or wire-like electrical connections from device to substrate
• CPC Class Codes: H01L 2225/06568 the devices decreasing in size, e.g. pyramidical stack
• CPC Class Codes: H01L 23/50 for integrated circuit devices, e.g. power bus, number of leadsH01L23/482 - H01L23/498 take precedence
• CPC Class Codes: H01L 23/645 Inductive arrangements H01L23/647, H01L23/66 take precedence
• CPC Class Codes: H01L 25/0657 Stacked arrangements of devices
• CPC Class Codes: H01L 25/16 the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
• CPC Class Codes: H01L 28/10 Inductors
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/30107 Inductance
• CPC Class Codes: H01L 2924/3011 Impedance
• CPC Class Codes: H02M 3/1584 with a plurality of power processing stages connected in parallel
• CPC Class Codes: H02M 3/1586 switched with a phase shift, i.e. interleaved

Abstract

A multi-chip module (MCM) is disclosed, which in some embodiments can include a packaging substrate, an interposer coupled to the substrate and having a power converter coupled to one or more vias, and a CMOS integrated circuit comprising one or more connecters aligned with and disposed proximate to the one or more vias to electrically couple the interposer to the integrated circuit. Methods of forming a voltage regulator on an interposer of a multi-chip module (MCM) are also provided.

Claims

1. A multi-chip module (MCM) comprising:

a packaging substrate;

an interposer coupled to the substrate, the interposer comprising a voltage regulator coupled to one or more vias; and

a CMOS integrated circuit comprising one or more connecters aligned with and disposed proximate to the one or more vias to thereby electrically couple the interposer to the integrated circuit.

2. The MCM of claim 1, wherein the interposer comprises silicon.

3. The MCM of claim 1, wherein the voltage regulator comprises one or more inductors.

4. The MCM of claim 3, wherein the one or more inductors comprises a plurality of inductors, each inductor coupled to one or more inductors proximate thereto.

5. The MCM of claim 4, wherein the plurality of inductors comprises an outer inductor joining a first end inductor to a second end inductor to symmetrically couple each inductor with a pair of neighboring inductors.

6. The MCM of claim 3, wherein the one or more inductors comprises four uncoupled two-turn inductors.

7. The MCM of claim 3, wherein the one or more inductors comprises eight single-turn coupled inductors.

8. The MCM of claim 3, wherein the one or more inductors comprises eight two-turn coupled inductors.

9. The MCM of claim 3, wherein one or more inductors comprises two sets of four single-turn coupled inductors.

10. The MCM of claim 3, wherein the voltage regulator comprises a buck converter coupled to the one or more inductors and configured to inversely couple the one or more inductors.

11. The MCM of claim 3, wherein the buck converter comprises a multi-phase buck converter, the MCM further comprising a power controller configured to provide power from the buck converter at a different phase corresponding to each of the one or more inductors.

12. A method of forming a voltage regulator on an interposer of a multi-chip module (MCM) comprising:

depositing on the interposer a magnetic alloy under a magnetic biasing field to form a plurality of magnetic cores including a top core and a bottom core;

inverse coupling adjacent magnetic cores of the plurality of magnetic cores;

forming copper windings about each of the plurality of magnetic cores;

forming one or more electrodes on the top magnetic core and on the bottom magnetic core;

electrically isolating the copper windings from the bottom magnetic core using a layer of barrier material;

electrically isolating the copper windings from the top magnetic core using a resist process;

joining the electrodes of bottom magnetic core and the top magnetic core to one or more respective pads on the interposer; and

forming vias through the interposer proximate the one or more pads.

13. The method of claim 12, further comprising wrapping an outer core around a first end magnetic core and a second end magnetic core to symmetrically couple each magnetic core with a pair of neighboring magnetic cores.

14. The method of claim 12, further comprising depositing top and bottom yokes corresponding to each magnetic core by electroplating.

15. The method of claim 14, wherein depositing the top and bottom yokes comprises plating the top and bottom yokes through photoresist-defined molds by through-mask plating.

16. The method of claim 15, further comprising

plating an area around each of the top and bottom yokes, and

separating each plated area with a resist frame.

17. The method of claim 15, wherein plating the top and bottom yokes comprises applying a magnetic field along an axis of the top and bottom yokes to define a magnetic anisotropy of the top and bottom yokes.

18. The method of claim 14, further comprising encapsulating the top and bottom yokes with a layer of dielectric material.

19. The method of claim 14, wherein forming the vias comprises opening a portion of the interposer proximate a point of contact of each top yoke with a corresponding bottom yoke by reactive ion etching.

20. The method of claim 12, wherein forming the copper windings comprises electroplating the copper windings through a resist mask.