INTERFACES AND DIE PACKAGES, AND APPARTUSES INCLUDING THE SAME

• US 20150043285A1
• Filed: 10/27/2014
• Published: 02/12/2015
• Est. Priority Date: 10/18/2011
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Min, Oh Seung
• Granted Patent: US 9,460,762 B2
• Time in Patent Office: Days
• US Class Current: 365/189.02
• CPC Class Codes: C23C 14/042 using masks
• CPC Class Codes: C23C 14/50 Substrate holders
• CPC Class Codes: C23C 16/042 using masks
• CPC Class Codes: C23C 16/4585 Devices at or outside the perimeter of the substrate support, e.g. clamping rings, shrouds
• CPC Class Codes: G11C 2213/71 Three dimensional array
• CPC Class Codes: G11C 5/02 Disposition of storage elements, e.g. in the form of a matrix array
• CPC Class Codes: G11C 7/10 Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
• CPC Class Codes: G11C 7/1012 Data reordering during input/output, e.g. crossbars, layers of multiplexers, shifting or rotating
• CPC Class Codes: G11C 7/1066 Output synchronization
• CPC Class Codes: G11C 7/1069 I/O lines read out arrangements
• CPC Class Codes: G11C 7/1084 Data input buffers, e.g. comprising level conversion circuits, circuits for adapting load
• CPC Class Codes: G11C 7/1093 Input synchronization
• CPC Class Codes: H01L 21/6734 specially adapted for supporting large square shaped substrates containers and packaging elements for glass sheets B65D85/48, transporting of glass products during their manufacture C03B35/00
• CPC Class Codes: H01L 21/67346 characterized by being specially adapted for supporting a single substrate or by comprising a stack of such individual supports
• CPC Class Codes: H01L 21/67706 Mechanical details, e.g. roller, belt H01L21/67709 takes precedence
• CPC Class Codes: H01L 21/67736 Loading to or unloading from a conveyor
• CPC Class Codes: H01L 21/681 using optical controlling means
• CPC Class Codes: H01L 21/682 Mask-wafer alignment in general G03F7/70, G03F9/70
• CPC Class Codes: H01L 21/6838 with gripping and holding devices using a vacuum; Bernoulli devices
• CPC Class Codes: H01L 2224/04042 Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
• CPC Class Codes: H01L 2224/05553 : being rectangular
• CPC Class Codes: H01L 2224/05554 : being square
• CPC Class Codes: H01L 2224/06155 : Covering only the peripheral area of the surface to be connected, i.e. peripheral arrangements
• CPC Class Codes: H01L 2224/32145 : the bodies being stacked
• CPC Class Codes: H01L 2224/32225 : the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/45099 : Material
• CPC Class Codes: H01L 2224/48106 : the connector being orthogonal to a side surface of the semiconductor or solid-state body, e.g. parallel layout
• CPC Class Codes: H01L 2224/48145 : the bodies being stacked
• CPC Class Codes: H01L 2224/48147 : with an intermediate bond, e.g. continuous wire daisy chain
• CPC Class Codes: H01L 2224/48225 : the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/48227 : connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/49175 : Parallel arrangements
• CPC Class Codes: H01L 2224/73265 : Layer and wire connectors
• CPC Class Codes: H01L 2225/06506 : Wire or wire-like electrical connections between devices
• CPC Class Codes: H01L 2225/0651 : Wire or wire-like electrical connections from device to substrate
• CPC Class Codes: H01L 2225/06562 : at least one device in the stack being rotated or offset
• CPC Class Codes: H01L 23/48 : Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
• CPC Class Codes: H01L 24/48 : of an individual wire connector
• CPC Class Codes: H01L 24/49 : of a plurality of wire connectors
• CPC Class Codes: H01L 24/73 : Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 25/18 : the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/1301 : Thyristor
• CPC Class Codes: H01L 2924/1434 : Memory
• CPC Class Codes: H01L 2924/15192 : Resurf arrangement of the internal vias
• CPC Class Codes: H01L 31/18 : Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof

Abstract

A memory device includes a memory die package including a plurality of memory dies, an interface device including an interface circuit, and a memory controller configured to control the interface with control data received from at least one of the plurality of memory dies. The interface device of the memory device is configured to divide and multiplex an IO channel between the memory die package and the memory controller into more than one channel using the control data receive from the at least one of the plurality of memory dies. The interface device for a memory device includes a control input buffer configured to receive an enable signal through a control pad, a first input buffer configured to receive a first data through a first IO pad in response to a first state of the enable signal, and a second input buffer configured to receive a second data through a second IO pad in response to a second state of the enable signal. The interface device further includes an input multiplexer configured to multiplex the first data and the second data to provide an input data.

Claims

1. An interface, comprising:

a control input buffer configured to receive an enable signal;

a first input buffer configured to receive a first data and provide a first input data;

a second input buffer configured to receive a second data and provide a second input data; and

an input multiplexer configured to multiplex the first input data and the second input data to provide integrated data in response to the enable signal.

2. The interface of claim 1, wherein the interface is configured to alternate receiving the first data through the first input buffer and receiving the second data through the second input buffer.

3. The interface of claim 1, further comprising:

a delay unit configured to delay to the integrated data; and

a latch unit configured to store the delayed integrated data.

4. The interface of claim 1, wherein the first input buffer is configured to receive a first die enable signal, and to provide the first input data in response to receiving the first die enable signal;

and wherein the second input buffer is configured to receive a second die enable signal, and to provide the second input data in response to receiving the second die enable signal.

5. The interface of claim 1, further comprising:

a first IO pad configured to receive the first data from a first group of die in a die package; and

a second IO pad configured to receive the second data from a second group of die in the die package.

6. A memory device, comprising:

a plurality of memory dies;

an interface comprising;

a control input buffer configured to receive an enable signal through a control pad from a first group of the plurality of memory dies, each of the first group of memory dies being coupled to the control pad;

a first input buffer configured to receive a first data through a first TO pad from the first group of memory dies, each of the first group of memory dies being coupled to the first TO pad;

a second input buffer configured to receive a second data through a second TO pad from a second group of the plurality of memory dies, each of the second group of memory dies being coupled to the second TO pad; and

an input multiplexer configured to multiplex the first data and the second data to provide integrated data in response to the enable signal.

7. An interface, comprising:

an output multiplexer configured to divide output data to provide a first data and a second data in response to an external control signal, the output multiplexer being further configured to provide a first control signal and a second control signal;

a first pre-driving circuit configured to provide a first pull-up signal and a first pull-down signal in response to the first data and the first control signal;

a first output buffer configured to provide a first output data in response to the first pull-up signal and the first pull-down signal;

a second pre-driving circuit configured to provide a second pull-up signal and a second pull-down signal in response to the second data and the second control signal; and

a second output buffer configured to provide a second output data in response to the second pull-up signal and the second pull-down signal.

8. The interface of claim 7, wherein the external control signal comprises a selection signal having a first state and a second state.

9. The interface of claim 8, wherein the output multiplexer is configured to provide the first data and the first control signal in response to the first state of the selection signal, and to provide the second data and the second control signal in response to the second state of the selection signal.

10. The interface of claim 7, further comprising:

a first TO pad configured to provide the first output data to a first group of dies in a die package; and

a second TO pad configured to provide the second output data to device second group of dies in the die package.

11. The interface of claim 7, wherein the output multiplexer is configured to receive a die enable signal as the external control signal, the die enable signal indicating enablement of a memory die in a die package.

12. The interface of claim 11, wherein the output multiplexer is further configured to determine whether the memory die indicated by the die enable signal is included in a first group of memory dies in the die package or in a second group of memory dies in the die package.

13. The interface of claim 12, wherein if the output multiplexer determines that the memory die indicated by the die enable signal is included in the first group of memory dies in the die package, the output multiplexer is configured to provide the first data and the first control signal.

14. The interface of claim 7, wherein the interface is to a plurality of memory dies.

15. The interface of claim 14, wherein the memory dies comprise at least one memory die selected from the group comprising:

a NAND memory die, a NOR memory die, a PCM memory die, a DRAM memory die, a SRAM memory die, a TRAM memory die, a RRAM memory die, and a MRAM memory die.

16. A memory device, comprising:

a plurality of memory dies;

an interface comprising;

an output multiplexer configured to divide the output data to provide a first data and a second data in response to an external control signal, the output multiplexer being further configured to provide a first control signal and a second control signal;

a first pre-driving circuit configured to provide a first pull-up signal and a first pull-down signal in response to the first data and the first control signal;

a first output buffer configured to provide a first output data in response to the first pull-up signal and the first pull-down signal through a first IO pad coupled to a first group of the plurality of memory dies;

a second pre-driving circuit configured to provide a second pull-up signal and a second pull-down signal in response to the second data and the second control signal; and

a second output buffer configured to provide a second output data in response to the second pull-up signal and the second pull-down signal through a second IO pad coupled to a second group of the plurality of memory dies.

17. An apparatus, comprising:

a controller interfaced to a plurality of dies divided into groups of dies;

respective I/O buses coupling the controller to each of the groups of dies, each I/O bus decoupled from the other groups of dies;

wherein the apparatus is configured to multiplex information exchanged with selected ones of the groups of dies on the respective I/O bus in response to a control signal.