POWER AMPLIFIER PROVIDING HIGH EFFICIENCY

• US 20150045095A1
• Filed: 08/01/2014
• Published: 02/12/2015
• Est. Priority Date: 08/06/2013
• Status: Active Grant

• Current Assignee: Ningbo AURA Semiconductor Company Limited
• Original Assignee: Aura Semiconductor Pvt., Ltd.
• Inventors: Somayajula, Shyam, D'Souza, Arnold J, Srinivasan, Hariharan
• Granted Patent: US 9,319,495 B2
• Time in Patent Office: Days
• US Class Current: 455/572
• CPC Class Codes: H03F 1/0227 using supply converters
• CPC Class Codes: H03F 2200/03 the amplifier being designed for audio applications
• CPC Class Codes: H03F 3/187 in integrated circuits
• CPC Class Codes: H03F 3/68 Combinations of amplifiers, e.g. multi-channel amplifiers for stereophonics power amplifiers using a combination of several semiconductor amplifiers H03F3/211; combinations of amplifiers using coupling networks with distributed constants H03F3/602
• CPC Class Codes: H04M 1/0202 Portable telephone sets, e.g. cordless phones, mobile phones or bar type handsets constructional features of telephone transmitters or receivers, e.g. of speakers or microphones H04M1/03

Abstract

A power amplifier containing a DC-DC converter, a linear amplifier and a control block. The DC-DC converter receives power from a power source and generates a regulated power supply voltage whose magnitude is controlled by the magnitude of a control signal provided to the DC-DC converter. The linear amplifier receives an input signal and generates a power-amplified output signal, and receives the regulated power supply voltage for operation. The control block is coupled to receive the input signal, and generates the control signal with a magnitude based on the amplitude of the input signal. The regulated power supply voltage is modulated based on the amplitude of the input signal, for peak-to-peak amplitudes of the power-amplified output greater than or less than or equal to the magnitude of the power source. High efficiency for the power amplifier is thereby obtained.

Claims

1. An Integrated Circuit (IC) comprising:

a DC-DC converter coupled to receive power from a power source and to generate a regulated power supply voltage as output, wherein a magnitude of said regulated power supply voltage is controlled by the magnitude of a control signal provided to said DC-DC converter;

a first linear amplifier coupled to receive a first input signal, said first linear amplifier designed to amplify said first input signal to generate a power-amplified output signal, wherein said first linear amplifier is coupled to receive said regulated power supply voltage for operation; and

a control block coupled to receive said first input signal, and to generate said control signal with a magnitude having positive correlation with an amplitude of said first input signal,

wherein the operation of said control block in conjunction with said DC-DC converter causes said regulated power supply voltage to vary based on said amplitude of said first input signal when the amplitude of said power-amplified output signal is in a first range less than a magnitude of said power source, as well as when the amplitude of said power-amplified output signal is in a second range greater than or equal to said magnitude of said power source.

2. The IC of claim 1, wherein said regulated power supply voltage is enabled to vary continuously based on said amplitude, said DC-DC converter designed to operate in a buck mode in one range of said amplitude and in a boost mode in another range of said amplitude, wherein said one range equals said first range and said another range equals said second range.

3. The IC of claim 2, wherein said control block generates a mode select signal indicating whether said DC-DC converter is to operate in said buck-mode or said boost-mode,

wherein said DC-DC converter is coupled to receive said mode select signal, and to operate in said buck-mode or said boost-mode based on the indication of said mode select signal,

whereby said regulated power supply voltage is enabled to vary based on said amplitude of said first input signal when said amplitude of said power-amplified output signal is in said first range, as well as when said amplitude of said power-amplified output signal is in said second range.

4. The IC of claim 3, wherein said amplitude of said power-amplified output signal represents a peak-to-peak amplitude of said power-amplified output signal, said IC further comprising:

a delay block coupled to receive a sequence of digital samples representing an analog signal, said delay block designed to delay each sample in said sequence of digital samples by a delay value, and to generate a sequence of delayed digital samples; and

a conversion block coupled to receive said sequence of delayed digital samples and to generate a corresponding analog signal as said first input signal,

wherein said control block comprises;

a first absolute value computation block coupled to receive said sequence of delayed digital samples, and to generate an absolute value of each sample in said sequence;

a digital to analog converter (DAC) is coupled to receive said absolute value and to convert said absolute value to a second analog signal; and

a smoothing filter coupled to receive said second analog signal, said smoothing filter designed to low-pass filter said second analog signal to generate a filtered signal, wherein said filtered signal is provided as said control signal.

5. The IC of claim 4, wherein said control block further comprises:

a headroom block coupled to receive said sequence of digital samples, said headroom block designed to generate a headroom value based on the envelope of the signal represented by said sequence of digital samples;

an adder block coupled to receive said headroom value and said absolute value, said adder block designed to generate a sum of said headroom value and said absolute value,

wherein said DAC is coupled instead to receive said sum and to convert said sum to said second analog signal.

6. The IC of claim 5, wherein said control block further comprises:

a slew tracker coupled to receive said sequence of digital samples, said slew tracker designed to determine a slew rate of the signal represented by said sequence of digital samples,

wherein, if said slew rate is greater than a threshold value, said DAC is coupled instead to receive a fixed code value and to convert said fixed code value to said second analog signal,

wherein, if said slew rate is greater than said threshold value, said DC-DC converter is operated in said boost mode.

7. The IC of claim 6, wherein said first input signal is a first audio signal representing a left channel of an audio system, said IC further comprising:

a second linear amplifier coupled to receive a second audio signal representing a right channel of said audio system, said second linear amplifier designed to amplify said second audio signal to generate another power-amplified output signal, wherein said second linear amplifier is coupled to receive said regulated power supply voltage for operation;

a second delay block coupled to receive a second sequence of digital samples representing said second audio signal, said second delay block designed to delay each sample in said second sequence of digital samples by said delay value, and to generate a second sequence of delayed digital samples; and

a second conversion block coupled to receive said second sequence of delayed digital samples and to generate said second audio signal,

wherein said control block further comprises;

a second absolute value computation block coupled to receive said second sequence of delayed digital samples, and to generate a second absolute value of each sample in said second sequence; and

a maximum value computation block to receive each of said absolute value and said second absolute value, and to a determine the greater of said absolute value and said second absolute value;

wherein said headroom block is coupled to receive said second sequence of digital samples, said headroom block designed, said headroom block designed to generate said headroom value based on the greater of the two envelopes of the respective signals represented by said sequence of digital samples and said second sequence of digital samples,

wherein said adder block is coupled instead to receive said greater of said absolute value and said second absolute value instead of said absolute value.

8. The IC of claim 7, wherein each of said first input signal, said power-amplified output signal, said second audio signal and said another power-amplified output signal is a differential signal.

9. The IC of claim 3, wherein said amplitude of said power-amplified output signal represents a peak-to-peak amplitude of said power-amplified output signal, wherein said control block is designed to compute an instantaneous amplitude of said first input signal, said IC further comprising:

a headroom tracker coupled to said power-amplified output signal, said headroom tracker block to generate a headroom value; and

a summation block,

wherein said summation block, instead of said control block, generates said control signal, said summation block to generate a sum of said headroom value and said instantaneous amplitude of said first input signal as said control signal.

10. The IC of claim 9, wherein said first input signal is a first audio signal representing a left channel of an audio system, said IC further comprising:

a second linear amplifier coupled to receive a second audio signal representing a right channel of said audio system, said second linear amplifier designed to amplify said second audio signal to generate another power-amplified output signal, wherein said second linear amplifier is coupled to receive said regulated power supply voltage for operation,

wherein said headroom tracker is coupled to said another power-amplified output signal,

wherein said headroom tracker comprises;

a maximum generator block to determine the greater of the instantaneous amplitudes of said power-amplified output signal and said another power-amplified output signal;

a subtraction block to generate a difference voltage between a magnitude of said regulated power supply voltage and said greater of the instantaneous amplitudes; and

an amplifier coupled to receive said difference voltage and a reference headroom voltage, and to generate said headroom value based on the difference between said difference voltage and said reference headroom voltage.

11. The IC of claim 10, wherein said headroom tracker further comprises:

a comparator to compare said difference voltage and a threshold headroom voltage, and to generate a binary value representing a comparison of said difference voltage and said threshold headroom voltage; and

a storage element to store said binary value,

wherein if said binary value indicates that said difference voltage is less than said threshold headroom voltage, said DC-DC converter is designed to either transition to class G operation or to generate said regulated power supply voltage with a fixed value.

12. The IC of claim 11, further comprising a conversion block to receive a sequence of digital samples representing an analog signal, said conversion block to generate a corresponding analog signal as said input signal.

13. The IC of claim 1, wherein said first linear amplifier is a single-supply amplifier powered only by said regulated power supply voltage, wherein each of said input signal and said power-amplified output signal is a differential signal, said first linear amplifier comprising:

a differential amplifier coupled to receive said input signal, and to provide said power-amplified output signal;

a first pair of resistors and a second pair of resistors to set a gain of said differential amplifier;

a third resistor and a fourth resistor coupled in series between a pair of output terminals across which said differential amplifier provides said power-amplified output signal;

a second differential amplifier coupled to receive a first voltage at a junction of said third resistor and said fourth resistor as one input, and a second voltage equal in magnitude to half the magnitude of said regulated power supply as a second input, wherein an output of said second differential amplifier sets a magnitude of a common mode voltage at each one of said pair of output terminals.

14. A method of operating a DC-DC converter comprised in a power amplifier, wherein said DC-DC converter is coupled to receive power from a power source and generates a regulated power supply as output, said power amplifier comprising a linear amplifier to receive an input signal and to generate a power-amplified output signal, said linear amplifier receiving said regulated power supply for operation, wherein said method is implemented in said power amplifier, said method comprising:

determining a magnitude of said input signal;

generating a control voltage with a magnitude having positive correlation with said magnitude of said input signal;

generating a mode select signal to indicate that said DC-DC converter is to operate in a buck-mode when an amplitude of said power-amplified output signal is less than a magnitude of said power source, said mode select signal to indicate that said DC-DC converter is to operate in a boost-mode when said amplitude of said power-amplified output signal is greater than or equal to said magnitude of said power source; and

operating said DC-DC converter to generate said regulated power supply according to said mode select signal and said control voltage,

wherein said regulated power supply voltage is enabled to vary continuously based on said magnitude of said input signal.

15. The method of claim 14, further comprising:

generating a headroom value representing a margin between the magnitude of said regulated power supply and a magnitude of said power-amplified output signal; and

adding a magnitude of said headroom value and said control voltage to generate a sum, wherein said operating varies said magnitude of said regulated power supply based on said sum.

16. The method of claim 15, wherein said operating maintains a constant difference between the amplitude of said regulated power supply and the amplitude of said power-amplified output signal, wherein said constant difference equals said headroom value.

17. The method of claim 16, wherein said magnitude of said headroom value has a positive correlation with a slew-rate of said input signal, said method further comprising:

delaying said input signal to generate a delayed input signal, wherein said linear amplifier power-amplifies said delayed input signal instead of said input signal,

wherein said control voltage is generated based on said delayed input signal, but wherein said headroom value is generated based on said input signal.

18. A mobile phone comprising:

a battery, a speaker, a processor and a power amplifier,

wherein said power amplifier comprises;

a DC-DC converter coupled to receive power from a power source and to generate a regulated power supply as output;

a linear amplifier coupled to receive an input signal from said processor and to generate a power-amplified output signal, wherein said power-amplified output signal is coupled to drive said speaker, wherein said linear amplifier receives said regulated power supply for operation,

wherein said power amplifier comprises;

means for determining a magnitude of said input signal;

means for generating a control voltage with a magnitude having positive correlation with said magnitude of said input signal;

means for generating a mode select signal to indicate that said DC-DC converter is to operate in a buck-mode when an amplitude of said power-amplified output signal is less than a magnitude of said power source, said mode select signal to indicate that said DC-DC converter is to operate in a boost-mode when said amplitude of said power-amplified output signal is greater than or equal to said magnitude of said power source; and

means for operating said DC-DC converter to generate said regulated power supply according to said mode select signal and said control voltage,

wherein said regulated power supply voltage is enabled to vary continuously based on said magnitude of said input signal.

19. The mobile phone of claim 18, wherein said power amplifier further comprises:

means for generating a headroom value representing a margin between the magnitude of said regulated power supply and a magnitude of said power-amplified output signal; and

means for adding a magnitude of said headroom value and said control voltage to generate a sum, wherein said operating varies said magnitude of said regulated power supply based on said sum.

20. The mobile phone of claim 19, wherein said means for operating maintains a constant difference between the amplitude of said regulated power supply and the amplitude of said power-amplified output signal, wherein said constant difference equals said headroom value,

wherein said magnitude of said headroom value has a positive correlation with a slew-rate of said input signal, said power amplifier further comprising:

means for delaying said input signal to generate a delayed input signal, wherein said linear amplifier power-amplifies said delayed input signal instead of said input signal,

wherein said control voltage is generated based on said delayed input signal, but wherein said headroom value is generated based on said input signal.